- 20 Nov, 2020 7 commits
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Jaehoon Chung authored
Exynos5440 SoC support has been dropped since commit 8c83315d ("ARM: dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY variant found in the Exynos5433 SoCs. Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased onto current kernel code, rewrote commit message] Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Acked-by:
Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by:
Jingoo Han <jingoohan1@gmail.com> Link: https://lore.kernel.org/r/20201120102627.14450-1-m.szyprowski@samsung.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Amelie Delaunay authored
Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by:
Amelie Delaunay <amelie.delaunay@st.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.comSigned-off-by:
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Neil Armstrong authored
The AXG Analog MIPI-DSI PHY also provides functions to the PCIe PHY, thus we need to have inclusive support for both interfaces at runtime. This fixes the regmap get from parent node, removes cell param to select a mode and implement runtime configuration & power on/off for both functions since they are not exclusive. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Remi Pommarel <repk@triplefau.lt> Link: https://lore.kernel.org/r/20201116101647.73448-4-narmstrong@baylibre.comSigned-off-by:
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Neil Armstrong authored
The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and MIPI DSI at the same time, and is not exclusive. Thus remove the invalid phy cell parameter. Signed-off-by:
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Neil Armstrong authored
The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI panels. Signed-off-by:
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Neil Armstrong authored
The PHY registers happens to be at the beginning of a large zone containing interleaved system registers (mainly clocks, power management, PHY control..), found in all Amlogic SoC so far. The goal is to model it the same way as the other "features" of this zone, like Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt and Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml and have a coherent bindings scheme over the Amlogic SoCs. This update the description, removed the reg attribute then updates the example accordingly. Signed-off-by:
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Neil Armstrong authored
The Amlogic AXg SoCs embeds a MIPI D-PHY to communicate with DSI panels, this adds the bindings. This D-PHY depends on a separate analog PHY. Signed-off-by:
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- 19 Nov, 2020 2 commits
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Rafał Miłecki authored
Initially this PHY driver was implementing MDIO access on its own. It was caused by lack of proper hardware design understanding. It has been changed back in 2017. DT bindings were changed and driver was updated to use MDIO layer. It should be really safe now to drop the old deprecated code. All Linux stored DT files don't use it for 3,5 year. There is close to 0 chance there is any bootloader with its own DTB using old the binding. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20201113113423.9466-1-zajec5@gmail.comSigned-off-by:
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Yangtao Li authored
For the current code, enable_pmu_unk1 only works in non-a83t and non-h6 types. So let's delete it from the sun50i_h6_cfg. Signed-off-by:
Yangtao Li <frank@allwinnertech.com> Link: https://lore.kernel.org/r/dc8cbb7b3cd59902a6719f207d18a232903fac8a.1604988979.git.frank@allwinnertech.comSigned-off-by:
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- 17 Nov, 2020 1 commit
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Vinod Koul authored
This reverts commit 3cc8e867 ("phy: amlogic: Replace devm_reset_control_array_get()") as it caused build failure drivers/soc/amlogic/meson-ee-pwrc.c: In function 'meson_ee_pwrc_init_domain': drivers/soc/amlogic/meson-ee-pwrc.c:416:65: error: expected ';' before 'if' Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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- 16 Nov, 2020 27 commits
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Jon Hunter authored
Deferred probe is an expected return value for devm_regulator_bulk_get(). Given that the driver deals with it properly, there's no need to output a warning that may potentially confuse users. Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Acked-by:
JC Kuo <jckuo@nvidia.com> Link: https://lore.kernel.org/r/20201111103708.152566-1-jonathanh@nvidia.comSigned-off-by:
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Florian Fainelli authored
Read the 'brcm,tx-amplitude-millivolt' property from Device Tree and propagate its value into the appropriate test transmit register to change the TX amplitude. Signed-off-by:
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Florian Fainelli authored
Document a new property which allows the selection of the SATA AFE TX amplitude in milli Volts. Possible values are 400, 500, 600 and 800mV. Acked-by:
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Amelie Delaunay authored
Change stm32-usbphyc driver to defer its probe when the expected reset control has its probe operation deferred. Signed-off-by:
Etienne Carriere <etienne.carriere@st.com> Signed-off-by:
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Amelie Delaunay authored
Change stm32-usbphyc driver to not print an error message when the device probe operation is deferred. Signed-off-by:
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Rikard Falkeborn authored
The only usage of tegra_xusb_pad_type and tegra_xusb_port_type is to assign their address to the type field in the device struct, which is a const pointer. Make them const to allow the compiler to put them in read-only memory. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20201109215844.167954-1-rikard.falkeborn@gmail.comSigned-off-by:
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Yejune Deng authored
devm_reset_control_array_get_exclusive() looks more readable Signed-off-by:
Yejune Deng <yejune.deng@gmail.com> Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/1604378274-6860-1-git-send-email-yejune.deng@gmail.comSigned-off-by:
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Swapnil Jakhade authored
Add Cadence Sierra PHY bindings in YAML format. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-17-git-send-email-chunfeng.yun@mediatek.comSigned-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/1604642930-29019-7-git-send-email-chunfeng.yun@mediatek.comSigned-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/1604642930-29019-5-git-send-email-chunfeng.yun@mediatek.comSigned-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource to simplify code Signed-off-by:
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Chunfeng Yun authored
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by:
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Manivannan Sadhasivam authored
SM8250 has multiple different PHY versions: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes QMP Modem PHY - 2 lanes Add support for these with relevant init sequence. In order to abstract the init sequence, this commit introduces secondary tables which can be used to factor out the unique sequence for each PHY while the former tables can have the common sequence. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201027170033.8475-3-manivannan.sadhasivam@linaro.orgSigned-off-by:
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Manivannan Sadhasivam authored
Add the below three PCIe PHYs found in SM8250 to the QMP binding: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes QMP Modem PHY - 2 lanes Signed-off-by:
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- 02 Nov, 2020 3 commits
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Lubomir Rintel authored
Add PHY driver for the HSICs found on Marvell MMP3 SoC. The driver is rather straightforward -- the PHY essentially just needs to be enabled. Signed-off-by:
Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200925235828.228626-4-lkundrak@v3.skSigned-off-by:
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Lubomir Rintel authored
I wrote this binding and I'm fine with it being GPL + BSD dual-licensed, as is recommended for new DT bindings. Signed-off-by:
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Lubomir Rintel authored
This has been added in error -- the PHY block doesn't have a reset pin. Signed-off-by:
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