- 18 Apr, 2023 40 commits
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Eric Yang authored
[Why] If optimized init is done in FW. DCN init can be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Dmytro Laktyushkin authored
[Why & How] Fix a typo for dcn315 line buffer bpp. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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Daniel Miess authored
[Why] 1. It could hit bandwidth limitdation under single dimm memory when connecting 8K external monitor. 2. IsSupportedVidPn got validation failed with 2K240Hz eDP + 8K24Hz external monitor. 3. It's better to filter out such combination in EnumVidPnCofuncModality 4. For short term, filter out in dc bandwidth validation. [How] Force 2K@240Hz+8K@24Hz timing validation false in dc. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Daniel Miess <Daniel.Miess@amd.com> Tested-by:
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Jingwen Zhu authored
[Why] The eDP retrain will cause the DPCD 300 to be reset to default. And cause the brightness can't be set correctly. [How] delete the call to edp panel power control in both enable_link_output/disable_link_output entirely and only call edp panel control in enable_link_dp and disable_link_dp once. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Jingwen Zhu <Jingwen.Zhu@amd.com> Tested-by:
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Michael Mityushkin authored
[Why] When link training during engine recovery, ASSR might fail causing panel mode to be reset to default. This should not happen for eDP as it will prevent the panel from turning back on. [How] Added dp_panel_mode to struct dc_link to remember previously applied panel mode. Do not reset panel mode to default while performing link training if previously used panel mode = eDP. Reviewed-by:
Michael Mityushkin <michael.mityushkin@amd.com> Tested-by:
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Dmytro Laktyushkin authored
[Why & How] Add options for dc odm debug. Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Alex Hung authored
[Why & How] timing.dsc_cfg.num_slices_v can be zero and it is necessary to check before using it. This fixes the error "divide error: 0000 [#1] PREEMPT SMP NOPTI". Reviewed-by:
Alex Hung <alex.hung@amd.com> Tested-by:
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Anthony Koo authored
- Add DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command - Remove d3 entry event and instead check for stream mask - dmu: Enable timeout recovery and detection for p-state Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Enable FPO + Vactive Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Since we do not use optimized watermark settings for MALL, set D = A - PMFW uses Set D for d0i3.1, so driver should make D = A for the time being - If we choose to optimize in the future we can set watermarks D correctly Reviewed-by:
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Michael Mityushkin authored
[Why] Doing core_link_disable_stream or set_dpms_off when reinitializing hardware causes issue to repro with external display connected. This is unnecessary, blanking pixel data should be sufficient. [How] Call disable_pixel_data while reinitializing hardware instead of core_link_disable_stream or set_dpms_off. Reviewed-by:
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Nasir Osman authored
[why] When we force ODM combine with DSC, we lose several 8 bit and 10 bit modes in validation and thus not able to use HDR. This is due to the number of horizontal slices used in DSC not properly being accounted for currently when 2:1 ODM Combine is forced. [how] Enforce at least two horizontal slices are used for DSC when ODM combine is forced. Reviewed-by:
Nasir Osman <nasir.osman@amd.com> Tested-by:
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Iswara Nagulendran authored
[HOW&WHY] Write DPCD 721 bit 7 to high, and the appropriate luminance level to DPCD 734-736 if bit 4 from DPCD register 734 is high, indicating that the panel luminance control is enabled from the panel side. Reviewed-by:
Iswara Nagulendran <Iswara.Nagulendran@amd.com> Tested-by:
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Rodrigo Siqueira authored
To ensure that FAMS can be used, DC must check if there is VRR support. This commit adds the required configuration to ensure FAMS can be executed in the target system. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Hersen Wu authored
[Why] hdcp are enabled for asics from raven. for old asics which hdcp are not enabled, hdcp_workqueue are null. some access to hdcp work queue are not guarded with pointer check. [How] add hdcp_workqueue pointer check before access workqueue. Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] If dmub command queuing fails due to the inbox being full, flush the inbox and resubmit the comamnd. This was previously the default behavior but was lost in a refactor. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Consolidate dmub access to a single interface. This makes it easier to add code in the future that needs to run every time a dmub command is requested (e.g. instrumentation, locking etc). Reviewed-by:
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Alvin Lee authored
[Description] - Having excessively large margin causes failure in the static schedulability check in some cases for SubVP + DRR - 100us of DRR margin is sufficient based on a weeks worth of stress testing on different display configs Reviewed-by:
Michael Strauss <Michael.Strauss@amd.com> Acked-by:
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Alvin Lee authored
[Description] - Previous bug fix for audio issue included dtbclk and p-state on the optimized boot path which is incorarect - We only care about DISPCLK in the optimized vs. non-optimized boot path to avoid audio issues Reviewed-by:
Saaem Rizvi <syedsaaem.rizvi@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Increse to 6 as that is the max surfaces supported asics can have. The is no practical use case yet, but this is valuable for pre-si validation. Reviewed-by:
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Hersen Wu authored
[Why] when amdgpu_dm_update_connector_after_detect is called two times successively with valid sink, memory allocated of aconnector->timing_requested for the first call is not free. this causes memeleak. [How] allocate memory only when aconnector->timing_requested is null. Reviewed-by:
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Aurabindo Pillai authored
[Why&How] When skipping full modeset since the only state change was a front porch change, the DC commit sequence requires extra checks to handle non existant plane states being asked to be removed from context. Reviewed-by:
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Alan Liu authored
[Why] Currently we don't check if secure display is enabled before we send command to disable secure display in dmub. It will accidentally cause some other igt tests to fail, eg, crtc-linear-degamma. [How] Refactor the code we reset the secure display state to check secure display was enabled or not before stopping it in dmub. Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Tested-by:
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Alex Hung authored
[Why] When IGT's kms_hdmi_inject forces EDID for HDMI audio, dc rejects the request because virtual signal is not in dc_is_audio_capable_signal function. [How] Includes SIGNAL_TYPE_VIRTUAL as audio capable. Reviewed-by:
Chao-kai Wang <Stylon.Wang@amd.com> Acked-by:
Wenchieh Chien <wenchieh.chien@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Add code path to copy dmub caps to dc, which is missing on dcn31 Acked-by:
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Rodrigo Siqueira authored
When the commit fff7eb56 ("drm/amd/display: Don't set dram clock change requirement for SubVP") was merged, we missed some parts associated with the MCLK switch. This commit adds all the missing parts. Fixes: fff7eb56 ("drm/amd/display: Don't set dram clock change requirement for SubVP") Reviewed-by:
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Wesley Chalmers authored
[WHY] It is possible to commit state multiple times in rapid succession with FAMS enabled; if each of these commits were to set optimized_required, then the user may see latency. [HOW] fw_based_mclk_switching is currently not used in dc->clk_mgr; use it to track whether the current state has FAMS enabled; if it has, then do not disable FAMS in prepare_bandwidth, and do not set optimized_required. Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by:
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Wesley Chalmers authored
[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. [HOW] Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets optimized_required. This change expects that Freesync requests are blocked when optimized_required is true. Reviewed-by:
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Leon Huang authored
[Why] set ABM pipe/backlight gets some issues when abm callback func pointers are NULL. For some usecase, driver would like to control PWM level before ABM resource is ready. However, recent flow refactor of ABM didn't consider that use case. [How] Rollback flow that sending inbox command to dmub directly when ABM function pointers aren't ready. Reviewed-by:
Leon Huang <Leon.Huang1@amd.com> Tested-by:
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Srinivasan Shanmugam authored
After reading from receiver via DPCD, check & log if it supports MST, DSC & FEC Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
The previous 'commit ca9beb8a ("drm/amd/display: Add logging when setting DP sink power state fails")', it is better to unconditionally print "failed to power up sink", because we are returning DC_ERROR_UNEXPECTED. Fixes: ca9beb8a ("drm/amd/display: Add logging when setting DP sink power state fails") Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Leon Huang authored
[Why] Refactor ABM feature and implement inbox command for DMUB. [How] Implement the ioctl to send inbox command to DMUB. Reviewed-by:
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Tom Rix authored
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dccg.c:277:6: warning: symbol 'dccg314_init' was not declared. Should it be static? This variable is only used in one file so should be static. Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
This commit replaces spaces with tabs in multiple functions and adjusts the indentation in some other parts of the code to improve readability. Reviewed-by:
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Rodrigo Siqueira authored
When using FPO, there is some misconfiguration that happens for the lack of configuration of the MCLK switch in some circumstances. This commit adds the required field update when using the MCLK switch. Reviewed-by:
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Rodrigo Siqueira authored
All clock values came from firmware, but bounding box values can be helpful in some debug situations. This commit updates some of the values associated with clock speed and memory channels. Reviewed-by:
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