- 16 Jul, 2020 4 commits
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Stephan Gerhold authored
Commit c240f29e ("arm64: dts: set the default i2c pin drive strength to 16mA") changed the default drive-strength for I2C pins in msm8916-pins.dtsi to the maximum possible (16 mA). While this makes sense for apq8016-sbc (DB410c) where you can connect an arbitrary amount of I2C devices with level shifters etc, there is no need to use a higher drive strength for other MSM8916 devices. The minimum drive strength (2 mA) seems to be totally sufficient to have everything work there. With the short pinctrl nodes introduced earlier we can easily override the drive-strength only for apq8016-sbc now. Use that and change the default back to 2 mA. i2c1_default/i2c5_default are already using 2 mA because they were added separately later and are not used in apq8016-sbc. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200622151751.408995-4-stephan@gerhold.netSigned-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Stephan Gerhold authored
So far we have been separating pinctrl entries into pinmux/pinconf. It turns out it is also possible to combine them: The advantage is that the device tree is overall more concise because the "pins" to configure just need to be specified once, not separately for pinmux/pinconf. Using the simpler form only for new entries would be rather confusing. This commit makes all MSM8916 device trees use the simplfied form. Signed-off-by:
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Stephan Gerhold authored
It is helpful to be able to see all hardware components in one part of the device tree, without having to scroll over the large amount of regulator/pinctrl nodes. Keep those separated at the end of the file to make navigation a bit easier. This also makes it consistent with the order used in apq8016-sbc.dtsi. Signed-off-by:
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Bjorn Andersson authored
Now that we don't need the intermediate syscon to represent the TCSR mutexes, update the dts to describe the TCSR mutex directly under /soc. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200622075956.171058-5-bjorn.andersson@linaro.orgSigned-off-by:
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- 15 Jul, 2020 2 commits
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Rakesh Pillai authored
The wlan firmware memory is statically mapped in the Trusted Firmware, hence the wlan driver does not need to map/unmap this region dynamically. Hence add the property to indicate the wlan driver to not map/unamp the firmware memory region dynamically. Also add the chain1 voltage supply for wlan. Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
Rakesh Pillai <pillair@codeaurora.org> Link: https://lore.kernel.org/r/1594615586-17055-1-git-send-email-pillair@codeaurora.orgSigned-off-by:
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Douglas Anderson authored
The WiFi supplies that were added recently can't have done anything useful because they were missing the "-supply" suffix. Booting without the "-supply" suffix would give these messages: ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-0.8-cx-mx not found, using dummy regulator ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-1.8-xo not found, using dummy regulator ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-1.3-rfa not found, using dummy regulator ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-3.3-ch0 not found, using dummy regulator Let's add the "-supply" suffix. Tested-by:
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- 14 Jul, 2020 1 commit
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Eric Biggers authored
Add the vendor-specific registers and clock for Qualcomm ICE (Inline Crypto Engine) to the device tree node for the UFS host controller on sdm845, so that the ufs-qcom driver will be able to use inline crypto. Use a separate register range rather than extending the main UFS range because there's a gap between the two, and the ICE registers are vendor-specific. (Actually, the hardware claims that the ICE range also includes the array of standard crypto configuration registers; however, on this SoC the Linux kernel isn't permitted to access them directly.) Signed-off-by:
Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20200710072013.177481-4-ebiggers@kernel.orgSigned-off-by:
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- 13 Jul, 2020 6 commits
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Rajendra Nayak authored
Add the power domain supporting performance state and the corresponding OPP tables for the sdhc device on sc7180. Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1593506712-24557-5-git-send-email-rnayak@codeaurora.orgSigned-off-by:
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Rajendra Nayak authored
Add the power domain supporting performance state and the corresponding OPP tables for the sdhc device on sdm845. Reviewed-by:
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Rajendra Nayak authored
qup has a requirement to vote on the performance state of the CX domain in sc7180 devices. Add OPP tables for these and also add power-domains property for all qup instances for uart and spi. i2c does not support scaling and uses a fixed clock. Reviewed-by:
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Rajendra Nayak authored
qup has a requirement to vote on the performance state of the CX domain in sdm845 devices. Add OPP tables for these and also add power-domains property for all qup instances for uart and spi. i2c does not support scaling and uses a fixed clock. Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1593506712-24557-2-git-send-email-rnayak@codeaurora.orgSigned-off-by:
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Rajendra Nayak authored
Add the power domain supporting performance state and the corresponding OPP tables for the qspi device on sc7180 Reviewed-by:
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Rajendra Nayak authored
Add the power domain supporting performance state and the corresponding OPP tables for the qspi device on sdm845 Reviewed-by:
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- 09 Jul, 2020 1 commit
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Sibi Sankar authored
Add OPP tables required to scale DDR/L3 per freq-domain on SDM845 SoCs. Tested-by:
Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200702204643.25785-1-sibis@codeaurora.orgSigned-off-by:
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- 08 Jul, 2020 1 commit
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Sibi Sankar authored
Having a non-MSA (Modem Self-Authentication) SID bypassed breaks modem sandboxing i.e if a transaction were to originate from it, the hardware memory protections units (XPUs) would fail to flag them (any transaction originating from modem are historically termed as an MSA transaction). Drop the unused non-MSA modem SID on SC7180 SoCs and cheza so that SMMU continues to block them. Tested-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by:
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- 02 Jul, 2020 2 commits
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Bjorn Andersson authored
Add a simple-mfd representing IMEM on SDM845 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Reviewed-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Bjorn Andersson authored
Add a simple-mfd representing IMEM on QCS404 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Reviewed-by:
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- 30 Jun, 2020 1 commit
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Sibi Sankar authored
Add OPP tables required to scale DDR/L3 per freq-domain on SC7180 SoCs. Reviewed-by:
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- 25 Jun, 2020 1 commit
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Akash Asthana authored
Add interconnect ports for GENI QUPs and QSPI to set bus capabilities. Signed-off-by:
Akash Asthana <akashast@codeaurora.org> Link: https://lore.kernel.org/r/1592908737-7068-9-git-send-email-akashast@codeaurora.orgSigned-off-by:
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- 24 Jun, 2020 1 commit
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Sivaprakash Murugesan authored
IPQ8074 has two super speed usb ports, add phy and dwc3 nodes to enable them. Signed-off-by:
Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1591625479-4483-6-git-send-email-sivaprak@codeaurora.orgSigned-off-by:
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- 23 Jun, 2020 17 commits
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Konrad Dybcio authored
Add properties required for the bootloader to select the correct bootloader blob. They have been removed from the SoC device tree as they should be set on a per-device basis. Signed-off-by:
Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623224813.297077-11-konradybcio@gmail.comSigned-off-by:
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Konrad Dybcio authored
Add PSCI node to enable multi-processor startup. Note that not every 8994 device firmware supports PSCI, and even if, then it can only start the cores and not shut them down. Signed-off-by:
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Konrad Dybcio authored
Add the CPU PMU to get perf support for hardware events. Signed-off-by:
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Konrad Dybcio authored
Add support for I2C and SPI buses to enable peripherals such as touchscreens or sensors. Also add DMA nodes, configuration and BLSP2 UART2 interface. Signed-off-by:
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Konrad Dybcio authored
Enable support for SDHCI on msm8994-based devices. Signed-off-by:
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Konrad Dybcio authored
Add a proper CPU map to enable the use of all 8 cores. Signed-off-by:
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Konrad Dybcio authored
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus. Signed-off-by:
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Konrad Dybcio authored
Following changes have been made: - remove name, compatible and msm-id - wrap clocks in clocks{} - order nodes by name and by address - clock_gcc -> gcc - msmgpio -> tlmm - qcom,smem -> smem - remove unit-address from smem - retire msm8994-pins.dtsi - add some of the missing pins - make comments C-style Signed-off-by: -
Bjorn Andersson authored
Add remoteproc nodes for the audio, compute and sensor cores, define glink for each one and enable them on the MTP with appropriate firmware defined. Reviewed-by:
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Bjorn Andersson authored
SMP2P is used for interrupting and being interrupted about remoteproc state changes related to the audio, compute and sensor subsystems. Reviewed-by:
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Bjorn Andersson authored
Add a node for the QMP AOSS. Reviewed-by:
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Bjorn Andersson authored
Add the IPCC node, used to send and receive IPC signals with remoteprocs. Reviewed-by:
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Bjorn Andersson authored
PM8150 ldo11 on the MTP is wired to VDD_SSC_CX and controlled in levels, rather than as a regulator. As such it's available from the rpmhpd as the SM8250_LCX power domain. Reviewed-by:
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Martin Botka authored
Add device tree support for the Sony Xperia 10 and 10 Plus smartphones. They are all based on the Sony Ganges platform (sdm630/636) and share a lot of common code. The differences are really minor, so a Ganges-common DTSI has been created to reduce clutter. 10 - Kirin 10 Plus - Mermaid This platform is based on SoMC Nile, but there are some major differences when it comes to pin configuration and panel setup (among others). The boards currently support: * Screen console * SDHCI * I2C * pstore log dump * GPIO keys * PSCI idle states Signed-off-by:
Martin Botka <martin.botka1@gmail.com> Signed-off-by:
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Konrad Dybcio authored
Add device tree support for the Sony Xperia XA2, XA2 Plus and XA2 Ultra smartphones. They are all based on the Sony Nile platform (sdm630) and share a lot of common code. The differences are really minor, so a Nile-common DTSI has been created to reduce clutter. XA2 - Pioneer XA2 Plus - Voyager XA2 Ultra - Discovery The boards currently support: * Screen console * SDHCI * I2C * pstore log dump * GPIO keys * PSCI idle states Signed-off-by:
Łukasz Patron <priv.luk@gmail.com> Link: https://lore.kernel.org/r/20200622192558.152828-6-konradybcio@gmail.comSigned-off-by:
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Konrad Dybcio authored
Add devicetree files for SDM630 SoC and its pin configuration. This commit adds basic nodes like cpu, psci and other required configuration for booting up from eMMC to the serial console. Signed-off-by:
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Konrad Dybcio authored
Add base DTS files for pm660(l) along with GPIOs, power-on and rtc nodes. Signed-off-by:
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- 21 Jun, 2020 3 commits
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Dmitry Baryshkov authored
Much like SDM845 each serial engine has 4 pins attached. Add all possible I2C and SPI nodes for all 20 serial engines. Tested-by:
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Bjorn Andersson authored
Add the TLMM pinctrl node for SM8250 and reserve pins 28-31 and 40-43 on the MTP as firmware does not allow Linux to touch these pins. Reviewed-by:
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Dmitry Baryshkov authored
Add temperature alarm and thermal zone configuration to all three pm8150 instances. Configuration is largely based on the msm-4.19 tree. These alarms use main adc of the pmic. Separate temperature adc is not supported yet. Signed-off-by:
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