- 26 Nov, 2020 18 commits
-
-
Nicolin Chen authored
According to Tegra X1 TRM, there are missing swgroups in the tegra210_swgroups list. So this patch adds them to the list. Note that the TEGRA_SWGROUP_GPU (in list) should be actually TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps TEGRA_SWGROUP_GPU (in list) as it is. Signed-off-by:
Nicolin Chen <nicoleotsuka@gmail.com> Acked-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201008003746.25659-6-nicoleotsuka@gmail.comSigned-off-by:
Krzysztof Kozlowski <krzk@kernel.org>
-
Dmitry Osipenko authored
EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201111011456.7875-9-digetx@gmail.comSigned-off-by:
-
Dmitry Osipenko authored
Add modularization support to the Tegra30 EMC driver, which now can be compiled as a loadable kernel module. Signed-off-by:
-
Dmitry Osipenko authored
The latency allowness is calculated based on buffering capabilities of memory clients. Add FIFO sizes to the Tegra30 memory clients. Signed-off-by:
-
Dmitry Osipenko authored
Add devfreq support to the Tegra20 EMC driver. Memory utilization statistics will be periodically polled from the memory controller and appropriate minimum clock rate will be selected by the devfreq governor. Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20201111011456.7875-5-digetx@gmail.comSigned-off-by:
-
Dmitry Osipenko authored
Remove IRQ number from error message since it doesn't add any useful information, especially because this number is virtual. Signed-off-by:
-
Dmitry Osipenko authored
Factor out clk initialization and make it resource-managed. This makes easier to follow code and will help to make further changes cleaner. Signed-off-by:
-
Dmitry Osipenko authored
The dev_pm_opp_get_opp_table() shouldn't be used by drivers, use dev_pm_opp_set_clkname() instead. Suggested-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
-
Dmitry Osipenko authored
Correct typo in a stub of devm_tegra_memory_controller_get() to fix a non-ARM kernel compile-testing. Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
-
Dmitry Osipenko authored
Now Internal and External Memory Controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. Signed-off-by:
-
Dmitry Osipenko authored
EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by:
-
Dmitry Osipenko authored
Add modularization support to the Tegra20 EMC driver, which now can be compiled as a loadable kernel module. Signed-off-by:
-
Dmitry Osipenko authored
Add common SoC-agnostic ICC framework which turns Tegra Memory Controller into a memory interconnection provider. This allows us to use interconnect API for tuning of memory configurations. Signed-off-by:
Peter Geis <pgwipeout@gmail.com> Tested-by:
Nicolas Chauvet <kwizart@gmail.com> Link: https://lore.kernel.org/r/20201104164923.21238-33-digetx@gmail.comSigned-off-by:
-
Dmitry Osipenko authored
Add missing PTC memory client latency allowness entry to the Tegra MC drivers. This prevents erroneous clearing of MC_INTSTATUS 0x0 register during of the LA programming in tegra_mc_setup_latency_allowance() due to the missing entry. Note that this patch doesn't fix any known problems. Signed-off-by:
-
Dmitry Osipenko authored
The platform_get_irq() prints error message telling that interrupt is missing, hence there is no need to duplicated that message in the drivers. Signed-off-by:
-
Dmitry Osipenko authored
Use devm_platform_ioremap_resource() helper which makes code a bit cleaner. Signed-off-by:
-
Dmitry Osipenko authored
Multiple Tegra drivers need to retrieve Memory Controller and there is duplication of the retrieval code among the drivers. Add new devm_tegra_memory_controller_get() helper to remove the code's duplication and to fix put_device() which was missed in the duplicated code. Make EMC drivers to use the new helper. Signed-off-by:
-
Krzysztof Kozlowski authored
Tegra SoC and clock controller changes for v5.11 Export symbols and add stubs necessary for upcoming modified Tegra memory controller drivers (touching also devfreq and interconnect). Signed-off-by:
-
- 06 Nov, 2020 15 commits
-
-
Dmitry Osipenko authored
Most of Host1x devices have at least one memory client. These clients are directly connected to the memory controller. The new interconnect properties represent the memory client's connection to the memory controller. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201104164923.21238-17-digetx@gmail.comSigned-off-by:
-
Dmitry Osipenko authored
Document EMC DFS OPP table and interconnect paths that will be used for scaling of system's memory bandwidth based on memory utilization statistics. Previously ACTMON was supposed to drive EMC clock rate directly, but now it should do it using interconnect framework in order to support shared voltage scaling in addition to the frequency scaling. Signed-off-by:
-
Dmitry Osipenko authored
Document new OPP table and voltage regulator properties which are needed for supporting dynamic voltage-frequency scaling of the memory controller. Some boards may have a fixed core voltage regulator, hence it's optional because frequency scaling still may be desired. Signed-off-by:
-
Dmitry Osipenko authored
External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns External Memory Controller into interconnect provider. Signed-off-by:
-
Dmitry Osipenko authored
Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by:
-
Dmitry Osipenko authored
Document new OPP table and voltage regulator properties which are needed for supporting dynamic voltage-frequency scaling of the memory controller. Some boards may have a fixed core voltage regulator, hence it's optional because frequency scaling still may be desired. Signed-off-by:
-
Dmitry Osipenko authored
External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns External Memory Controller into interconnect provider. Signed-off-by:
-
Dmitry Osipenko authored
Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by:
-
Dmitry Osipenko authored
The SoC core voltage can't be changed without taking into account the clock rate of External Memory Controller. Document OPP table that will be used for dynamic voltage frequency scaling, taking into account EMC voltage requirement. Document optional core voltage regulator, which is optional because some boards may have a fixed core regulator and still frequency scaling may be desired to have. Signed-off-by:
-
Dmitry Osipenko authored
External Memory Controller is interconnected with memory controller and with external memory. Document new interconnect property which turns EMC into interconnect provider. Signed-off-by:
-
Dmitry Osipenko authored
Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by:
-
Dmitry Osipenko authored
Tegra20 External Memory Controller talks to DRAM chips and it needs to be reprogrammed when memory frequency changes. Tegra Memory Controller sits behind EMC and these controllers are tightly coupled. This patch adds the new phandle property which allows to properly express connection of EMC and MC hardware in a device-tree, it also put the Tegra20 EMC binding on par with Tegra30+ EMC bindings, which is handy to have. Signed-off-by:
-
Dmitry Osipenko authored
Drivers that use tegra_sku_info and have COMPILE_TEST are failing to be build due to the missing stub for tegra_sku_info. Signed-off-by:
-
Dmitry Osipenko authored
The tegra_read_ram_code() is used by EMC drivers and we're going to make these driver modular, hence this function needs to be exported. Signed-off-by:
-
Dmitry Osipenko authored
We're going to modularize Tegra EMC drivers and some of the EMC-clock driver symbols need to be exported. Signed-off-by:
-
- 05 Nov, 2020 1 commit
-
-
Dmitry Osipenko authored
There is superfluous zero in the registers base address and registers size should be twice bigger. Signed-off-by:
-
- 27 Oct, 2020 4 commits
-
-
Nicolin Chen authored
According to Tegra X1 TRM, there are missing swgroups in the tegra210_swgroups list. So this patch adds them in bindings. Note that the TEGRA_SWGROUP_GPU (in list) should be actually TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps TEGRA_SWGROUP_GPU (in list) as it is. Signed-off-by:
-
Nicolin Chen authored
Cleanup the list of swgroups (ordering by register address) to prepare for new ones. Signed-off-by:
-
Nicolin Chen authored
Some def values are mismatched with Tegra X1 TRM, probably because being copied from tegra124.c file. Signed-off-by:
-
Nicolin Chen authored
According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field [23:16] of register at address 0x3e0 with a reset value of 0x80 at register 0x3e0, while bit-1 of register 0xb98 is for enable bit of seswr. Signed-off-by:
-
- 25 Oct, 2020 2 commits
-
-
Linus Torvalds authored
-
Joe Perches authored
Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Conversion done using the script at: https://lore.kernel.org/lkml/75393e5ddc272dc7403de74d645e6c6e0f4e70eb.camel@perches.com/2-convert_section.plSigned-off-by:Joe Perches <joe@perches.com> Reviewed-by:
Nick Desaulniers <ndesaulniers@gooogle.com> Reviewed-by:
Miguel Ojeda <ojeda@kernel.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
-
