- 12 Oct, 2020 7 commits
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Sean Paul authored
In commit 79946723 ("drm/i915: Assume 100% brightness when not in DPCD control mode"), we fixed the brightness level when DPCD control was not active to max brightness. This is as good as we can guess since most backlights go on full when uncontrolled. However in doing so we changed the semantics of the initial 'backlight.enabled' value. At least on Pixelbooks, they were relying on the brightness level in DP_EDP_BACKLIGHT_BRIGHTNESS_MSB to be 0 on boot such that enabled would be false. This causes the device to be enabled when the brightness is set. Without this, brightness control doesn't work. So by changing brightness to max, we also flipped enabled to be true on boot. To fix this, make enabled a function of brightness and backlight control mechanism. Fixes: 79946723 ("drm/i915: Assume 100% brightness when not in DPCD control mode") Cc: Lyude Paul <lyude@redhat.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Kevin Chowski <chowski@chromium.org>> Signed-off-by:
Sean Paul <seanpaul@chromium.org> Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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Imre Deak authored
The DP Standard's recommendation is to use the LTTPR non-transparent mode link training if LTTPRs are detected, so let's do this. Besides power-saving, the advantages of this are that the maximum number of LTTPRs can only be used in non-transparent mode (the limit is 5-8 in transparent mode), and it provides a way to narrow down the reason for a link training failure to a given link segment. Non-transparent mode is probably also the mode that was tested the most by the industry. The changes in this patchset: - Pass the DP PHY that is currently link trained to all LT helpers, so that these can access the correct LTTPR/DPRX DPCD registers. - During LT take into account the LTTPR common lane rate/count and the per LTTPR-PHY vswing/pre-emph limits. - Switch to LTTPR non-transparent LT mode and train each link segment according to the sequence in DP Standard v2.0 (complete CR/EQ for each segment before continuing with the next segment). v2: - Switch to non-transparent mode during connector detection, which is required before reading the per-PHY LTTPR capabilities. - Move the DP_PHY_LTTPR() macro to drm_dp_helper.h (Ville) - Use the new drm_dp_dpcd_read_phy_link_status() instead of adding the same logic to intel_dp_get_link_status(). (Ville) - Make intel_dp_lttpr_phy_caps() return a pointer to the whole array instead of a pointer to its first element. (Ville) - Add the intel_dp_phy_is_downstream_of_source() helper. (Ville) - Add a code comment about the disable->enable quirk of non-transparent mode. - Add the intel_dp_training_pattern_set_reg() helper. - Fix checkpatch/sparse warns. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201007170917.1764556-7-imre.deak@intel.com
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Imre Deak authored
By default LTTPRs should be in transparent link training mode, nevertheless in this patch we switch to this default mode explicitly. The DP Standard recommends this, supposedly because an LTTPR may be left in the non-transparent mode (by BIOS, previous kernel, or after reset due to a firmware bug). I haven't seen this happening, but let's follow the DP Standard. v2: - Add a code comment about the explicit disabling of non-transparent mode. v3: - Move check to prevent initing LTTPRs on eDP to init_dp_lttpr_init(). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
Add the helpers and register definitions needed to read out the common and per-PHY LTTPR capabilities and perform link training in the LTTPR non-transparent mode. v2: - Add drm_dp_dpcd_read_phy_link_status() and DP_PHY_LTTPR() here instead of adding these to i915. (Ville) v3: - Use memmove() to convert LTTPR to DPRX link status format. (Ville) Cc: dri-devel@lists.freedesktop.org Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Imre Deak authored
To prepare for a follow-up LTTPR change factor out a helper to disable the training pattern in DPCD. We'll need to do this for each LTTPR (without programming the port to output the idle pattern) when training in LTTPR non-transparent mode. While at it also move the disable-link-training logic from intel_dp_set_link_train() to intel_dp_stop_link_train(), since the latter is the only user of this. v2: - Move the disable-link-training logic to intel_dp_stop_link_train() (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
Split the prepare, link training, fallback-handling steps into their own functions for clarity and as a preparation for the upcoming LTTPR changes. While at it also: - Unexport and inline intel_dp_set_idle_link_train(), which is used at a single place. - Add some documentation to functions that are exported or that can use a better description about which part of the LT sequence they implement. v2: (Ville) - Unexport/inline intel_dp_set_idle_link_train() - Make the documentation of intel_dp_prepare_link_train()/intel_dp_stop_link_train() more accurate wrt. HW specific details. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
An LTTPR can be trained with training pattern 4 even if the DPCD revision is < 1.4, but drm_dp_training_pattern_mask() would change pattern 4 to pattern 3 on those DPCD revisions. Since intel_dp_training_pattern() makes already sure that the proper training pattern is used, all that needs to be masked out is the scrambling disable flag, which is or'd to the mask later based on the training pattern. v2: - Use a helper instead of open-coding the masking. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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- 10 Oct, 2020 3 commits
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Matt Roper authored
The updated bspec forcewake table also provides us with new multicast ranges that should be reflected in our workaround code. Note that there are different types of multicast registers with different styles of replication and different steering registers. The i915 MCR range lists we're updating here are only used to ensure we can verify workarounds properly (i.e., if we can't steer register reads we don't want to verify workarounds where an unsteered read might hit a fused-off instance of the unit). Because of this, we don't need to include any of the multicast ranges where all instances of the register will always present and fusing doesn't play a role. Specifically, that means that we are not including the MCR ranges designated as "SQIDI" in the bspec. Bspec: 66696 Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201009194442.3668677-4-matthew.d.roper@intel.comReviewed-by:
José Roberto de Souza <jose.souza@intel.com>
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Matt Roper authored
The bspec's forcewake page was very stale and out of date for recent platforms. The hardware team finally provided us with an updated gen12 table (which applies to TGL, RKL, and DG1) and there are a lot of changes. v2: - Add comments showing the subregions of ranges that we've combined for ease of code review. (Jose) - Rebase on the s/FORCEWAKE_BLITTER/FORCEWAKE_GT/ patch Bspec: 66696 Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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Matt Roper authored
The power well that we've been referring to as the 'blitter' well is actually more of a general GT power well which contains a lot of things other than the blitter engine registers. The FORCEWAKE_BLITTER name in the code was used for historic reasons, but no longer matches how the bspec describes this power well and just causes confusion for people not familiar with this area of the code. Let's rename it to FORCEWAKE_GT to more accurately describe the role of the power well and match how the modern bspec refers to it. v2: - Add a comment noting that the GT power well includes the blitter engine. (Jose) Bspec: 66696, 66534, 67609 Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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- 09 Oct, 2020 16 commits
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José Roberto de Souza authored
Another step towards PSR2 selective fetch, here programming plane selective fetch registers and MAN_TRK_CTL enabling selective fetch but for now it is fetching the whole area of the planes. The damaged area calculation will come as next and final step. v2: - removed warn on when no plane is visible in state - removed calculations using plane damaged area in intel_psr2_program_plane_sel_fetch() v3: - do not shift 16 positions the plane dst coordinates, only src is shifted v4: - only setting PLANE_SEL_FETCH_CTL_ENABLE and MCURSOR_MODE in PLANE_SEL_FETCH_CTL v5: - not masking bits for cursor BSpec: 55229 Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201007195238.53955-3-jose.souza@intel.com
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José Roberto de Souza authored
Due to the debugfs flag, has_psr2 in CRTC state could have a different value than psr.psr2_enabled and it was causing PSR2 subfeatures(DC3CO and selective fetch) to be set to not a expected state. So here only taking in consideration the parameter and debugfs flag when computing PSR state, this way the CRTC state will also have the correct state. intel_psr_fastset_force() was already broken as intel_psr_compute_config() was already only enabling PSR when psr_global_enabled() and all other PSR requirements are met. So some changes was required in this function, now it iterates over all connectors, if it is a eDP connector and is active force a modeset in the CRTC driving this connector, what will cause the new PSR state to be set based on the debugfs flag. v2: - end connector iterator in error cases Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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José Roberto de Souza authored
For platforms without selective fetch this register is reserved so do not write 0 to it. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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José Roberto de Souza authored
This will be used in future but already adding to VBT so we are updated with VBT changes. Reviewed-by:
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José Roberto de Souza authored
This will remove the "Expected child device config size for VBT version 235 not known" debug message seen in TGL, although this is not fixing anything it good to keep our VBT parser updated. Reviewed-by:
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José Roberto de Souza authored
Child min_brightness is obsolete from VBT 234+, instead the new min_brightness field in the main structure should be used. This new field is 16 bits wide, so backlight_precision_bits is needed to check if value needs to be scaled down but it is only available in VBT 236+ so working around it by using the also new backlight_level in the main struct. v2: - missed that backlight_data->level is also obsolete v3: - s/backlight/brightness to better match specification - using u16 to specify brightness level instead of a u32 : 16 BSpec: 20149 Reviewed-by:
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Ville Syrjälä authored
ggtt offsets/alignments are u32 everywhere else. Don't use a signed int for them here. Signed-off-by:
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Ville Syrjälä authored
when the hardware isn't going to use the aux plane there's no real point in dealing with the relevant hardware restrictions. So let's just skip all that when not necessary. We can now also remove the offset=~0xfff behaviour for unused color planes. Let's just zero out everyting so as to not leave stale garbage behind to confuse people debugging the code. v2: Explicitly set AUX_DIST to zero when there is no aux plane Reviewed-by: Imre Deak <imre.deak@intel.com> #v1 Signed-off-by:
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Ville Syrjälä authored
When the number of potential color planes grew to 4 we stopped setting all unused color plane offsets to ~0xfff. The code still tries to do this, but actually does nothing since the loop limits are bogus. skl_check_main_surface() actually depends on this ~0xfff behaviour as it will make sure to move the main surface offset below the aux surface offset because the hardware AUX_DIST must be a non-negative value [1], and for simplicity it doesn't bother checking if the AUX plane is actually needed or not. So currently it may end up shuffling the main surface around based on some stale leftover AUX offset. The skl+ plane code also just blindly calculates the AUX_DIST whether or not the AUX plane is actually needed by the hw or not, and that too will now potentially use some stale AUX surface offset in the calculation. Would seem nicer to guarantee a consistent non-negative AUX_DIST always. So bring back the original ~0xfff offset behaviour for unused color planes. Though it doesn't seem super likely that this inconsistency would cause any real issues. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Fixes: 2dfbf9d2 ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") Signed-off-by:
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Ville Syrjälä authored
i915_{save,restore}_state() are actually all about the display. Currently they are split into display part + SWF part. But since the SWF part is also related to the display let's just move that part into its own thing and flip the roles around so that the current display part is the main function. Signed-off-by:Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
As with eDP and LVDS we should also respect the power cycle delay on DSI panels. We are not using the power sequencer for these, and we have no optimizations around the sleep duration, so we just msleep() the whole thing away. Note that the ICL+ DSI code doesn't seem to have any power off/power cycle delay handling whatsoever. The only thing it handles is the power on delay. As that looks pretty busted in general I won't bother dealing with it for the time being. Signed-off-by:
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Ville Syrjälä authored
Just like with eDP let's wait for the power sequencer power cycle delay before we reboot the machine, as otherwise we can't guarantee the panel's minimum power cycle delay will be respected. Signed-off-by:
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Ville Syrjälä authored
Extend the eDP panel power cycle delay wait on reboot handling to cover all platforms. No reason to think that VLV/CHV are in any way special since the documentation states that the hardware power cycle delay goes back to its default value on reset, and that may not be enough for all panels. Signed-off-by:
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Ville Syrjälä authored
Currently VLV/CHV use a reboot notifier to make sure the panel power cycle delay isn't violated across a system reboot. Replace that with the new encoder .shutdown() hook. And let's also stop overriding the power cycle delay with the max value. No idea why the current code does that. The already programmed delay should be correct. Signed-off-by:
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Ville Syrjälä authored
Add a new encoder hook .shutdown() which will get called at the end of the pci .shutdown() hook. We shall use this to deal with the panel power cycle delay issues. Signed-off-by:
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Ville Syrjälä authored
Implement the pci .shutdown() hook in order to quiesce the hardware prior to reboot. The main purpose here is to turn all displays off. Some displays/other drivers tend to get confused if the state after reboot isn't exactly as they expected. One specific example was the Dell UP2414Q in MST mode. It would require me to pull the power cord after a reboot or else it would just not come back to life. Sadly I don't have that at hand anymore so not sure if it's still misbehaving without the graceful shutdown, or if we managed to fix something else since I last tested it. For good measure we do a gem suspend as well, so that we match the suspend flow more closely. Also stopping all DMA and whatnot is probably a good idea for kexec. I would expect that some kind of GT reset happens on normal reboot so probably not totally necessary there. v2: Use the pci .shutdown() hook instead of a reboot notifier (Lukas) Do the gem suspend for kexec (Chris) Cc: Lukas Wunner <lukas@wunner.de> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:Chris Wilson <chris@chris-wilson.co.uk>
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- 07 Oct, 2020 9 commits
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Matt Roper authored
As with RKL, DG1's VBT outputs are indexed according to PHY rather than DDI. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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Matt Roper authored
As with RKL, DG1's PHY C acts as a comp master for PHY D. Bspec: 49291 Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201007002210.3678024-7-lucas.demarchi@intel.com
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Matt Roper authored
The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec details for that bit tell us that it need only be set for PHY-A and PHY-B. It also turns out that there isn't even an instance of the PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL logic that conditionally skips PHY_MISC usage to DG1 as well. Bspec: 50107 Cc: Aditya Swarup <aditya.swarup@intel.com> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by:
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Lucas De Marchi authored
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC. From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9 mapping as in ICL/TGL. The values for VBT seem wrong in BSpec. For the current boards we actually have a 1:1 mapping. BSpec: 49311, 49945, 20124 Cc: Aditya Swarup <aditya.swarup@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Venkata Sandeep Dhanalakota authored
On DGFX the register range has been extended to go up to 8MB. However we only actually use up to address 280000h, so let's increase it to 4MB. v2 (Lucas): add bspec reference and reword commit message to explain the 4 vs 8 MB used (requested by Matt Roper) Bspec: 53616 Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by:
Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com> Signed-off-by:
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Lucas De Marchi authored
DG1 has a new MOCS table. We still use the old definition of the table, but as for any dgfx card it doesn't contain the control_value values (these values don't matter as we won't program them). Bspec: 45101 v2: Reword the comment to state that the last few entries are reserved instead of "the last two". DG1 reserves four instead of two from previous platforms (from Matt Roper) Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: -
Matt Roper authored
DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz frequencies on CNP+. Note that register bits associated with this frequency confusingly use 37 for the divider field rather than 38 as you might expect. For simplicity, let's just assume that this 38.4 MHz frequency will hold true for other future platforms with "fake" PCH south displays and that the CNP-style behavior will remain for other platforms with a real PCH. Bspec: 49950 Bspec: 49309 Cc: Aditya Swarup <aditya.swarup@intel.com> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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Lucas De Marchi authored
Synchronize with the current list of DG1 PCI IDs. Signed-off-by:
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José Roberto de Souza authored
Recent update in documentation defeatured eDP HBR3 for EHL and JSL. v2: - Remove dead code in ehl_get_combo_buf_trans() v3: - Rebase BSpec: 32247 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by:
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- 06 Oct, 2020 5 commits
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Imre Deak authored
Apply Display WA #22010492432 for combo PHY PLLs too. This should fix a problem where the PLL output frequency is slightly off with the current PLL fractional divider value. I haven't seen an actual case where this causes a problem, but let's follow the spec. It's also needed on some EHL platforms, but for that we also need a way to distinguish the affected EHL SKUs, so I leave that for a follow-up. v2: - Apply the WA at one place when calculating the PLL dividers from the frequency and the frequency from the dividers for all the combo PLL use cases (DP, HDMI, TBT). (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
Atm, if a full modeset is performed during the initial modeset the link training will happen with uninitialized max DP rate and lane count. Make sure the corresponding encoder state is initialized by adding an encoder hook called during driver init and system resume. A better alternative would be to store all states in the CRTC state and make this state available for the link re-training code. Also instead of the DPCD read in the hook there should be really a proper sink HW readout in place. Both of these require a bigger rework, so for now opting for this minimal fix to make at least full initial modesets work. The patch is based on https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3 v2: (Ville) - s/sanitize_state/sync_state/ - No point in calling the hook when CRTC is disabled, remove the call. - No point in calling the hook for MST, remove it. v3: Check only DPCD_REV to avoid clobbering intel_dp->dpcd. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
Some BIOSes set an unsupported/imprecise DP link rate (for instance on TGL A stepping). Make sure that we do an encoder recompute and a modeset in this case. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
Move the checks to decide whether a fastset is possible during the initial commit to an encoder hook. This check is really encoder specific and the next patch will also require this adding a DP encoder specific check. v2: Fix negated condition in gen11_dsi_initial_fastset_check(). v3: Make sure to call the hook for all encoders on the crtc. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
The BIOS of at least one ASUS-Z170M system with an SKL I have programs the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with bit#0 incorrectly set. This happens with the "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9 HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1 WRPLL parameters (assuming PDIV=7 was the intended setting). This corresponds to 262749 PLL frequency/port clock. Later the driver sets the same mode for which it calculates the same dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding). Based on the above, let's assume that PDIV=7 was intended and the HW just ignores bit#0 in the PDIV register field for this setting, treating 100b and 101b encodings the same way. While at it add the MISSING_CASE() for the p0,p2 divider decodings. v2: (Ville) - Add a define for the incorrect divider value. - Emit only a debug message when detecting the incorrect divider value. - Use fallthrough from the incorrect divider value case. - Add the MISSING_CASE()s. v3: Return 0 freq for incorrect divider values. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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