- 03 Oct, 2019 16 commits
-
-
Bhawanpreet Lakha authored
This module manages HDCP for amdgpu driver. The module behaves as a state machine which handles the different authentication states of HDCP The module is divided into 3 major components +--------+ | Hdcp.c | +--------+ Manages the state machine, sends the events to be executed and communicates with the dm +-----------+ |Execution.c| +-----------+ This executes events based on the current state. Also generates execution results as transition inputs +------------+ |Transition.c| +------------+ Decides the next state based on the input and makes requests to hdcp.c to handle. +-------------+ ------> | Execution.c | ------ | +-------------+ | | V +----+ +--------+ +--------------+ | DM | -----> | Hdcp.c | <------------ | Transition.c | +----+ <----- +--------+ +--------------+ v2: Drop unused function definitions Signed-off-by:Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Bhawanpreet Lakha authored
DTM is the display topology manager. This is needed to communicate with psp about the display configurations. This patch adds -Loading the firmware -The functions and definitions for communication with the firmware v2: Fix formatting Signed-off-by: -
Bhawanpreet Lakha authored
This patch adds -Loading the firmware -The functions and definitions for communication with the firmware v2: Fix formatting Signed-off-by:
-
Aric Cyr authored
[Why] There can be some unsynchronized frames when entering/exiting LFC. This may cause tearing or stuttering at such transitions. [How] Add a enter/exit margin to algorithm to smoothly transition into and out of LFC without desynchronizing frames. Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Reza Amini <Reza.Amini@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com> Signed-off-by:
-
Dmytro Laktyushkin authored
Detile buffer size affects dcc caps and therefore needs to be corrected for each ip. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
-
Martin Leung authored
tg_inst may be used uninitialized, so initialize it to 0. Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
Jaehyun Chung <Jaehyun.Chung@amd.com> Acked-by:
-
Aric Cyr authored
Signed-off-by:
-
Zhan Liu authored
[Why] When more than 2 displays are connected to the graphics card, only the minimum memory clock is needed. However, when more displays are connected, the minimum memory clock is not sufficient enough to support the overwhelming bandwidth. System will hang under this circumstance. Also, the old code didn't address HBM cards, which has 2 pseudo channels. We need to add the HBM part here. [How] When graphics card connects to 2 or more displays, switch to high memory clock. Also, choose memory multiplier based on whether its regular DRAM or HBM. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
-
Aric Cyr authored
Signed-off-by:
-
Martin Leung authored
[why] seamless boot didn't work for non edp's before [how] removed edp-specific code, made dp read uefi-set link settings. Also fixed a hubbub code line to be consistent with usage of function. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
-
Dmytro Laktyushkin authored
Previously 8k30 worked with dsc and odm combine due to a workaround that ran the formula a second time with dsc support enable should dsc validation fail. This worked when clocks were low enough for formula to enable odm to lower voltage, however now broke due to increased clocks. This change updates the ODM combine policy within the formula to properly reflect our current policy within DC, only enabling ODM when we have to, as well as adding a check for viewport width when dsc is enabled. As a side effect the redundant call to dml when odm is required is now unnecessary. Signed-off-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
-
Wesley Chalmers authored
[WHY] Presently, there is no way for clocks to be lowered, only raised. [HOW] Compare clock status against previous known clock status, and optimize if different. This requires re-ordering the layout of the dc_clocks structure, as the current ordering allows identical clock states to appear different. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
-
Nikola Cornij authored
[why] Some ODM-related register settings are inconsistently updated by VBIOS, causing the state in DC to be invalid, which would then end up crashing in certain use-cases (such as disable/enable device). [how] Check the enabled status of the second pipe when determining the number of OPTC sources. If the second pipe is disabled, set the number of sources to 1 regardless of other settings (that may not be updated correctly). Signed-off-by:
-
Anthony Koo authored
[Why] A lot of the time, the backlight characteristic curve maps min backlight to a non-zero value. But there are cases where we want the curve to intersect at 0. In this scenario even if OS never asks to set 0% backlight, the ABM reduction can result in backlight being lowered close to 0. This particularly can cause problems in some LED drivers, and in general just looks like backlight is completely off. [How] Add default cap to disallow backlight from dropping below 1% even after ABM reduction is applied. Signed-off-by:
-
Wesley Chalmers authored
[WHY] This change was made because DTO programming was double-buffered, which is itself an issue. After deactivating the DTO double buffer, this change becomes unnecessary. Signed-off-by:
-
Wesley Chalmers authored
[WHY] When changing DPP global ref clock, DTO adjustments must take effect immediately, or else underflow may occur. It appears the original decision to double-buffer DTO adjustments was made to prevent underflows that occur when raising DPP ref clock (which is not double-buffered), but that same decision causes similar issues when lowering DPP global ref clock. The better solution is to order the adjustments according to whether clocks are being raised or lowered. Signed-off-by:
-
- 17 Sep, 2019 13 commits
-
-
Julian Parkin authored
[Why] Separating the hardware initialization from the creation of the dc structures gives greater flexibility to the dm to override options for debugging. [How] Move the hardware initialization call to a new function, dc_hardware_init. No functional change is intended. Signed-off-by:
Julian Parkin <julian.parkin@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by:
-
Lewis Huang authored
[Why] I2C write command always send mot = true will cause sink state incorrect. [How] 1. Remove default i2c write mot = true. 2. Deciding mot flag by is_end_of_payload flag. Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
-
Martin Tsai authored
[Why] The new implementation changed the behavior to allow process setMode to DAL when DAL returns empty mode query for unplugged display. This will trigger additional disable_link(). When unplug HDMI from MST dock, driver will update stream->signal to "Virtual". disable_link() will call disable_output() if the signal type is not DP and induce other displays on MST dock show black screen. [How] Don't need to process disable_output() if the signal type is virtual. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
-
Dmytro Laktyushkin authored
dcn20_calculate_dlg_params was incorrectly indexing pipe src and dst structs when extracting global sync params. Signed-off-by:
-
Dmytro Laktyushkin authored
Global sync update was missing vtg update resulting in underflow if vstartup decreased a significant amount. Signed-off-by:
-
Stylon Wang authored
[Why] Even if YUV420 is available for video mode, YUV444 is still automatically selected. This poses a problem for compliance tests. [How] Add a per-connector debugfs entry "force_yuv420_output" to force selection of YUV420 mode. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
-
Dmytro Laktyushkin authored
Surface dchub/dpp update would not trigger if a stream update was the only cause. This change now allows stream flags to trigger this update. Signed-off-by:
-
Wesley Chalmers authored
[WHY] A function to adjust DPP clocks with DTO already exists; function code is identical to the code replaced here Signed-off-by:
-
Mikita Lipski authored
[why] The issue is specific for linux, as on timings such as 8K@60 or 4K@144 DSC should be working in combination with ODM Combine in order to ensure that we can run those timings. The validation for those timings was passing, but when pipe split was happening second pipe wasn't being programmed. [how] Rebuild mapped resources if we split stream for ODM. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Acked-by:
-
Aric Cyr authored
Signed-off-by:
-
Josip Pavic authored
[Why] Current configuration 0 is just a placeholder, and final parameters needed. Also, configuration 1 is expected to emulate ABM 2.1 but is too aggressive. [How] Redefine configuration 0 with the finalized parameters, and increase the contrast gain of configuration 1 so that it properly emulates ABM 2.1. Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
-
Ilya Bakoulin authored
[Why] Secondary viewport dimension/position registers are not programmed, which can cause issues in some stereo configurations. [How] Add register definitions and register programming. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
-
Christian König authored
The placement is something TTM/BO internal and the RAS code should avoid touching that directly. Add a helper to create a BO at a fixed location and use that instead. v2: squash in fixes (Alex) Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
-
- 16 Sep, 2019 11 commits
-
-
Andrey Grodzovsky authored
Fix checksum calculation after manually resetting the table. Unify reset and empty EEPROM init flow. Protect the table reset with lock. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
-
Guchun Chen authored
Use debugfs_remove_recursive to remove the whole debugfs directory instead of removing the node one by one. Signed-off-by:
-
Christian König authored
This is usfull for debugging. Signed-off-by:
-
Christian König authored
Already done in the CPU based backend code. Signed-off-by:
-
Christian König authored
No functional change. Signed-off-by:
-
Christian König authored
This reverts commit a213c2c7. The changes to fix this should have landed in 5.1. Signed-off-by:
Zhou, David(ChunMing) <David1.Zhou@amd.com> Signed-off-by:
-
Jiange Zhao authored
With changes in PSP and HV, SRIOV VF will handle vram gtt location just like bare metal. There is no need to differentiate it anymore. Signed-off-by:
Jiange Zhao <Jiange.Zhao@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
-
Aaron Liu authored
These is no LBPW on Renoir. So removing program of lbpw for renoir. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
-
Jay Cornwall authored
ttmp[4:5] hold information useful to the debugger. Use ttmp[14:15] instead, aligning implementation with gfx9 trap handler. Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
shaoyun liu <Shaoyun.liu@amd.com> Signed-off-by:
-
zhong jiang authored
debugfs_remove and kfree has taken the null check in account. hence it is unnecessary to check it. Just remove the condition. No functional change. This issue was detected by using the Coccinelle software. Signed-off-by:
zhong jiang <zhongjiang@huawei.com> Signed-off-by:
-
Jean Delvare authored
It is fine for displays without audio functionality to not provide any SAD block in their EDID. Do not log an error in that case, just return quietly. Inspired by a similar fix to the amdgpu driver in the context of bug fdo#107825: https://bugs.freedesktop.org/show_bug.cgi?id=107825Signed-off-by:
Jean Delvare <jdelvare@suse.de> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
-
