- 10 Aug, 2022 21 commits
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Rodrigo Siqueira authored
DCN314 has multiple references to FPU operations inside the resource files, and we need to move those codes to the DML folder. This commit creates the dcn314_fpu files and moves the bounding box operation to this file. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Daniel Miess authored
[Why] DP DSC YCbCr422 not working because dcn314_calculate_dccg_k1_k2_values does not account for two pixels per container [How] Replace the contents of dcn314_calculate_dccg_k1_k2_values with the code from the function dcn32_calculate_dccg_k1_k2_values Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Daniel Miess <Daniel.Miess@amd.com> Tested-by:
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Tim Huang authored
The EnableGfxOff message is dropped from the new PMFW ppsmc interface. Signed-off-by:
Tim Huang <tim.huang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Tim Huang authored
Update the SmuMetrics_t defination and SMU driver interface version. Signed-off-by:
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Tim Huang authored
Enable GFX CG gate/ungate control. Signed-off-by:
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Tim Huang authored
Add below GFX Clock Gating supports: 1. GFX Coarse Grain Clock Gating(CGCG) 2. GFX Coarse grain light sleep/deep sleep(CGLS) 3. GFX Medium Grain Clock Gating(MGCG) 4. GFX Fine Grain Clock Gating(FGCG) 5. Repeater Fine Grain Clock Gating 6. Perfmon Clock Gating Signed-off-by:
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Yifan Zhang authored
GC version is 11.0.1 rather than 11.0.2 Signed-off-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Ma Jun authored
Remove redundant reference of header file dev_printk.h Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Lijo Lazar authored
A list of devices to be reset is already created in amdgpu_device_gpu_recover function. Creating another list with the same nodes is incorrect and not supported in list_head. Instead, pass the device list as part of reset context. Fixes: 9e085647 (drm/amdgpu: Refactor mode2 reset logic for v13.0.2) Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Magali Lemes authored
Add missing headers to solve the following warnings from sparse: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:656:17: warning: symbol 'ddr4_wm_table_gs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:693:17: warning: symbol 'lpddr4_wm_table_gs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:730:17: warning: symbol 'lpddr4_wm_table_with_disabled_ppt' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:767:17: warning: symbol 'ddr4_wm_table_rn' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:804:17: warning: symbol 'ddr4_1R_wm_table_rn' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:841:17: warning: symbol 'lpddr4_wm_table_rn' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.c:217:17: warning: symbol 'ddr4_wm_table' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.c:254:17: warning: symbol 'lpddr5_wm_table' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.c:53:30: warning: symbol 'dcn3_1_ip' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.c:197:30: warning: symbol 'dcn3_15_ip' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.c:293:30: warning: symbol 'dcn3_16_ip' was not declared. Should it be static? Fixes: 1a340825 ("drm/amd/display: move FPU code on dcn21 clk_mgr") Fixes: 5085e036 ("drm/amd/display: move FPU code from dcn301 clk mgr to DML folder") Fixes: 26f4712a ("drm/amd/display: move FPU related code from dcn31 to dml/dcn31 folder") Fixes: fa896297 ("drm/amd/display: move FPU related code from dcn315 to dml/dcn31 folder") Fixes: 3f8951cc ("drm/amd/display: move FPU related code from dcn316 to dml/dcn31 folder") Signed-off-by:
Magali Lemes <magalilemes00@gmail.com> Reviewed-by:
Maíra Canal <mairacanal@riseup.net> Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Likun Gao authored
Update the vram width algorithm for vram_info v3_0 to align with the changes of latest IFWI. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Daniel Phillips authored
Separately accumulate a statistic of rounded up allocations to use to report availability, with a view to increasing the likelihood a buffer object can be successfully allocated at exactly the size reported by the availability API. Signed-off-by:
Daniel Phillips <daniel.phillips@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Daniel Phillips authored
Rounding up allocations in the allocation path caused test regressions, so now just round in the availability path. Signed-off-by:
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Magali Lemes authored
Since "rn_clk_mgr.h" needs ‘struct clk_mgr_internal’ which is declared in "clk_mgr_internal.h", include "clk_mgr_internal.h" in "rn_clk_mgr.h" instead of in its source file. Because of the change above, change the order of '#include "rn_clk_mgr.h"', so that the necessary structs are visible to dcn20_clk_mgr.h. Signed-off-by:
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Magali Lemes authored
As "dcn3_1_soc", "dcn3_15_soc", and "dcn3_16_soc" are not used outside of their corresponding "dcn3*_fpu.c", make them static and remove their extern declaration. Fixes: 26f4712a ("drm/amd/display: move FPU related code from dcn31 to dml/dcn31 folder") Fixes: fa896297 ("drm/amd/display: move FPU related code from dcn315 to dml/dcn31 folder") Fixes: 3f8951cc ("drm/amd/display: move FPU related code from dcn316 to dml/dcn31 folder") Signed-off-by:
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Magali Lemes authored
There are two identical CFLAGS entries for "display_mode_vba_20.o", so remove one of them. Also, as there's already an entry for "display_mode_lib.o" CFLAGS, regardless of CONFIG_DRM_AMD_DC_DCN being defined or not, remove the one entry between CONFIG_DRM_AMD_DC_DCN ifdef guards. Signed-off-by:
André Almeida <andrealmeid@igalia.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
This reverts commit bac4b41d. This commit was a part of a patchset responsible for reducing the stack size. However, after some other changes, this commit becomes unnecessary, so we are reverting it here. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by:
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Rodrigo Siqueira authored
This reverts commit c3b3f9ba. This commit was a part of a patchset responsible for reducing the stack size. However, after some other changes, this commit becomes unnecessary, so we are reverting it here. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reported-by:
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Rodrigo Siqueira authored
Revert "drm/amd/display: reduce stack for dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport" This reverts commit 3c3abac6. This commit was a part of a patchset responsible for reducing the stack size. However, after some other changes, this commit becomes unnecessary, so we are reverting it here. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reported-by:
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Rodrigo Siqueira authored
This reverts commit 86e4863e. This commit was a part of a patchset responsible for reducing the stack size. However, after some other changes, this commit becomes unnecessary, so we are reverting it here. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reported-by:
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Aurabindo Pillai authored
[Why&How] Add the missing definition to set the register field HBLANK_MINIMUM_SYMBOL_WIDTH Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
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- 03 Aug, 2022 1 commit
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Dave Airlie authored
Merge tag 'amd-drm-next-5.20-2022-07-29' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.20-2022-07-29: amdgpu: - Misc spelling and grammar fixes - DC whitespace cleanups - ACP smatch fix - GFX 11.0 updates - PSP 13.0 updates - VCN 4.0 updates - DC FP fix for PPC64 - Misc bug fixes amdkfd: - SVM fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220729202742.6636-1-alexander.deucher@amd.com
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- 29 Jul, 2022 7 commits
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Rodrigo Siqueira authored
We got a report from Stephen/Michael that the PowerPC build was failing with the following error: ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float ld: failed to merge target specific data of file drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o This error happened because of the function optc3_set_vrr_m_const. This function expects a double as a parameter in a code that is not allowed to have FPU operations. After further investigation, it became clear that optc3_set_vrr_m_const was never invoked, so we can safely drop this function and fix the ld issue. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Melissa Wen <mwen@igalia.com> Reported-by:
Michael Ellerman <mpe@ellerman.id.au> Tested-by:
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Xiaojian Du authored
This patch will enable support for psp 13.0.4 blcok. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
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Xiaojian Du authored
This patch will add files for PSP 13.0.4. Signed-off-by:
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Xiaojian Du authored
This patch will add header files for MP 13.0.4. Signed-off-by:
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Yifan Zhang authored
This patch corrects RLC_RLCS_BOOTLOAD_STATUS offset and index for GC 11.0.1. Signed-off-by:
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Xiaojian Du authored
This patch will make SMU send msg to IMU for the front-door loading, it is required by some ASICs. Signed-off-by:
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Yu Zhe authored
time_is_before_jiffies deals with timer wrapping correctly. Signed-off-by:
Yu Zhe <yuzhe@nfschina.com> Signed-off-by:
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- 28 Jul, 2022 11 commits
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Jonathan Kim authored
Hives that require psp topology info to be reflected will leak hive reference so fix it. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by:
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Evan Quan authored
The feature is ready with latest firmwares. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
And get the version bumped to 0x2C to match the latest PMFW. Signed-off-by:
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Jack Xiao authored
mes self test rely on vm mapping, move it after drm sched re-started so that vm mapping can work during gpu reset. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-and-tested-by:
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Evan Quan authored
This extra call trace dump comes out in every gpu reset. And it gives people a wrong impression that something went wrong. Although actually there was not. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Sonny Jiang authored
Not enable VCN pg because encode issue Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Sonny Jiang authored
Enable support for vcn_4_0_2 video codec Signed-off-by:
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Sonny Jiang authored
Add VCN_4_0_2 firmware support Signed-off-by:
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Sonny Jiang authored
Add function to support VCN_4_0_2 doorbell Signed-off-by:
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Sonny Jiang authored
The return value should be set in vcn4 boot poll. Signed-off-by:
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Chengming Gui authored
Add PSP_V13 memory training support funcs. v2: replace DRM_{DEBUG/ERROR} with dev_{dbg/err}. (Hawking) v3: fix checkpatch error (Alex) Signed-off-by:Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
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