- 19 Jun, 2018 2 commits
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Souptick Joarder authored
Use new return type vm_fault_t for fault handler. For now, this is just documenting that the function returns a VM_FAULT value rather than an errno. Once all instances are converted, vm_fault_t will become a distinct type. Ref-> commit 1c8f4220 ("mm: change return type to vm_fault_t") Previously vm_insert_{mixed,pfn} returns err which driver mapped into VM_FAULT_* type. The new function vmf_insert_{mixed,pfn} will replace this inefficiency by returning VM_FAULT_* type. Signed-off-by:
Souptick Joarder <jrdr.linux@gmail.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Souptick Joarder authored
Use new return type vm_fault_t for fault handler in vm_operations_struct. Signed-off-by:
Matthew Wilcox <mawilcox@microsoft.com> Reviewed-by:
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- 15 Jun, 2018 38 commits
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Mikita Lipski authored
Initially FBC would be initialized if display's edid was correct and all the modes acquired from it, but n case when edid is corrupted or non-existant we must still initialize FBC. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Eric Bernstein authored
Number of OPPs to be instantiated is based on number of timing generators, not number of pipes. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Eric Bernstein authored
Remove setting DP_DB_DISABLE to avoid issues when changing bit depth after vbios take over. Refactor code to perform single register update for both pixel encoding and component depth fields. Signed-off-by:
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Alvin lee authored
Signed-off-by:
Alvin lee <alvin.lee3@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Vitaly Prosyak authored
It is used when curve register settings are generated by 'matlab', i.e. bypass color module calculation. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Krunoslav Kovac authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Krunoslav Kovac authored
Signed-off-by:
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Krunoslav Kovac authored
Signed-off-by:
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Krunoslav Kovac authored
Signed-off-by:
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Harry Wentland authored
We'd like to use some of them in dc_link_ddc and amdgpu_dm and should have them available in dc_ddc_types.h. Signed-off-by:
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Eric Bernstein authored
Update stream encoder based on feedback from HW team. Signed-off-by:
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Mikita Lipski authored
Extract edid's checksum and send it back for verification if EDID_TEST is requested. Also added a flag for EDID checksum write in TEST_RESPONSE structure, and simple spelling fix. Signed-off-by:
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Mikita Lipski authored
Provide the connector with a single fail-safe mode of 640x480 for CTS tests instead of providing a list of possible base modes. Signed-off-by:
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Andrey Grodzovsky authored
Add documentation for missed parameters. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Michel Dänzer authored
This was accidentally dropped by the "drm/amdgpu: update documentation for amdgpu_irq.c v3" change, resulting in the GPUVM documentation body being included twice in the generated documentation. Trivial. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Rex Zhu authored
driver need to know the real power source to do some power related configuration when initialize. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
driver need to update uvd/vce smc table before enable uvd/vce dpm. Reviewed-by:
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Rex Zhu authored
1. move ac_power to struct pm from dpm, so can be shared with powerplay 2. remove power_source in powerplay, use adev->pm.ac_power instand. 3. update ac_power before dispatch power task. Reviewed-by:
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Rex Zhu authored
As the SAMU ip was not supported in linux, so delete the SAMU support in powerplay on asics Bonarire/Hawwii/Tonga/Fiji/Polaris/vegam. Reviewed-by:
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Alex Deucher authored
Document the hwmon and power control interfaces exposed by the amdgpu driver. v2: use section rather than chapter for now Reviewed-by:
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Andrey Grodzovsky authored
Move all instnaces of this check into a function in amdgpu_gmc.h Rename the original function to a more proper name. v2: Add more places to cleanup. Reviewed-by:
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Slava Abramov authored
Add/update function level documentation and add reference to amdgpu_irq.c in amdgpu.rst v2: Added DOC comment Added more explanations for amdgpu_hotplug_work_func Properly formatted unused parameters Properly formatted return values Fixed usage of acronyms More consistent styling v3: Removed duplicate "not" Using '&' to refer to functions and types Signed-off-by:
Slava Abramov <slava.abramov@amd.com> Acked-by:
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Andrey Grodzovsky authored
Add/update function level documentation and add reference to amdgpu_vm.c in amdgpu.rst v2: Fix reference in rst file. Fix compilation warnings. Add space between function names and params list where it's missing. v3: Fix some funtion comments. Add formatted documentation to structs. Signed-off-by:
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Slava Abramov authored
In doc comments for struct amdgpu_mn: destrution -> destruction Signed-off-by:
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Christian König authored
And wire it up as well. v2: improve the wording, fix label mismatch Signed-off-by:
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Christian König authored
Just a copy&paste leftover from radeon. v2: rebase (Alex) Signed-off-by:
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Harry Wentland authored
DC has an upcoming change that requires these to read the board layout. Signed-off-by:
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Junwei Zhang authored
Don't need validation list any more Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
David Zhou <david1.zhou@amd.com> Reviewed-by:
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David Panariti authored
SQ can generate interrupts and installs the ISR to handle the SQ interrupts. Add parsing SQ data in interrupt handler. v2: Remove CZ only limitation. Rebase. Signed-off-by:
David Panariti <David.Panariti@amd.com> Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by:
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David Panariti authored
SQ can generate interrupts on EDC/ECC errors and this struct controls how the interrupt is handled. The guts are filled in in the gf_v<major>_<minor>.c files. v2: Rebase. Signed-off-by:
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David Panariti authored
ISR will DRM_ERROR ECC error message. v2: Remove CZ only limitation. Rebase. Signed-off-by:
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Shirish S authored
This patch is extends the usage of WB in gfx8's ib test which was originally implemented in the below upstream patch "ed9324af drm/amdgpu: change gfx9 ib test to use WB" For reference below are the reasons for switching to WB: 1)Because when doing IB test we don't want to involve KIQ health status affect, and since SCRATCH register access is go through KIQ that way GFX IB test would failed due to KIQ fail. 2)acccessing SCRATCH register cost much more time than WB method because SCRATCH register access runs through KIQ which at least could begin after GPU world switch back to current Guest VF Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Emily Deng authored
For buffer object that has shadow buffer, need twice commands. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Boyuan Zhang authored
Add AMDGPU_HW_IP_VCN_JPEG to queue mgr Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
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Boyuan Zhang authored
Add AMDGPU_HW_IP_VCN_JPEG to info query Signed-off-by:
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Boyuan Zhang authored
Add AMDGPU_HW_IP_VCN_JPEG define for jpeg CS Signed-off-by:
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Boyuan Zhang authored
Enable vcn jpeg ib ring test in amdgpu_ib.c Signed-off-by:
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