- 11 Apr, 2023 1 commit
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Bhupesh Sharma authored
Document the Qualcomm qrb4210-rb2 board based on Robotics version of the Snapdragon SM4250 Soc, i.e. QRB4210. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230411072840.2751813-2-bhupesh.sharma@linaro.org
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- 07 Apr, 2023 5 commits
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Manivannan Sadhasivam authored
To align with rest of the devicetree files, let's move the "status" property to the end of the nodes. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230331145915.11653-2-manivannan.sadhasivam@linaro.org
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Manivannan Sadhasivam authored
The reset and wake properties in the PCIe EP node belong to the board dts as they can be customized per board design. So let's move them from SoC dtsi. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230331145915.11653-1-manivannan.sadhasivam@linaro.org
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Kathiravan T authored
Document the MI01.6 (Reference Design Platform 468) board based on IPQ5332 family of SoCs. Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230323093120.20558-2-quic_kathirav@quicinc.com
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Lux Aliaga authored
Document the Xiaomi Mi A3 (xiaomi-laurel-sprout) smartphone which is based on the Snapdragon 665 SoC. Signed-off-by:
Lux Aliaga <they@mint.lgbt> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230306170817.3806-6-they@mint.lgbt
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Konrad Dybcio authored
Document QRB210, a QRB version of QCM2290. Document QTI Robotics RB1 as a QRB2210 device. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230403-topic-rb1_qcm-v2-2-dae06f8830dc@linaro.org
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- 06 Apr, 2023 2 commits
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Alex Elder authored
Move a few device tree "status" properties so that they are the last specified property, in "qcom-sdx65-mtp.dts" and "qcom-sdx65.dtsi". Note that properties must always be specified before sub-nodes. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Suggested-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Alex Elder <elder@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327195605.2854123-3-elder@linaro.org
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Alex Elder authored
Add IPA-related nodes and definitions to "sdx65.dtsi". The SMP2P nodes (ipa_smp2p_out and ipa_smp2p_in) are already present. Enable IPA in "sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Tested-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by:
Alex Elder <elder@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327195605.2854123-2-elder@linaro.org
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- 04 Apr, 2023 2 commits
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Yang Xiwen authored
Add a compatible for Yiming LTE dongle uz801-v3.0 Signed-off-by:
Yang Xiwen <forbidden405@foxmail.com> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/tencent_61B4697855AD14BA2930AC7B21FFC75C4406@qq.com
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Yang Xiwen authored
Henan Yiming Technology Co., Ltd. was established in 2021. The business scope of the company includes: communication equipment (excluding radio control equipment). Link: https://gw.yimingkeji.netSigned-off-by:
Yang Xiwen <forbidden405@foxmail.com> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/tencent_27DD0718C3FD9C5F7D6E2FBA225CAA760405@qq.com
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- 22 Mar, 2023 1 commit
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Krzysztof Kozlowski authored
syscon should not be used alone as compatible. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230306072618.10770-2-krzysztof.kozlowski@linaro.org
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- 16 Mar, 2023 10 commits
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Manivannan Sadhasivam authored
To align with rest of the devicetree files, let's move the "status" property down Suggested-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308082424.140224-11-manivannan.sadhasivam@linaro.org
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Manivannan Sadhasivam authored
Enable PCIe RC support on Thundercomm T55 board. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308082424.140224-10-manivannan.sadhasivam@linaro.org
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Manivannan Sadhasivam authored
To align with the rest of the devicetree files and the relative properties, let's list the values of properties such as {reg/clock/interrupt}-names vertically. Suggested-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308082424.140224-9-manivannan.sadhasivam@linaro.org
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Manivannan Sadhasivam authored
The PCIe controller in SDX55 can act as the RC controller also. Let's add support for it. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308082424.140224-8-manivannan.sadhasivam@linaro.org
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Manivannan Sadhasivam authored
There is only one PCIe PHY in this SoC, so there is no need to add an index to the suffix. This also matches the naming convention of the PCIe controller. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308082424.140224-7-manivannan.sadhasivam@linaro.org
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Manivannan Sadhasivam authored
Unit address of PCIe EP node should be 0x1c00000 as it has to match the first address specified in the reg property. This also requires sorting the node in the ascending order. Fixes: e6b69813 ("ARM: dts: qcom: sdx55: Add support for PCIe EP") Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308082424.140224-6-manivannan.sadhasivam@linaro.org
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Manivannan Sadhasivam authored
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses (0x0fe00000, 0x31e00000, 0x35e00000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 93241840 ("ARM: dts: qcom: Add pcie nodes for ipq8064") Reported-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230228164752.55682-17-manivannan.sadhasivam@linaro.org
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 18751940 ("ARM: dts: ipq4019: Add a few peripheral nodes") Reported-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230228164752.55682-16-manivannan.sadhasivam@linaro.org
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Manivannan Sadhasivam authored
To maintain the uniformity, let's use the 0x prefix for the values of ranges property. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230228164752.55682-15-manivannan.sadhasivam@linaro.org
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Devi Priya authored
Document the new ipq9574 SoC/board device tree bindings Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Devi Priya <quic_devipriy@quicinc.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230214163116.9924-6-quic_devipriy@quicinc.com
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- 15 Mar, 2023 7 commits
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Rayyan Ansari authored
Change the XO clock in MSM8974's GCC node to point to RPMCC. Signed-off-by:
Rayyan Ansari <rayyan@ansari.sh> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230121192540.9177-4-rayyan@ansari.sh
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Rayyan Ansari authored
Add the XO and Sleep Clock sources to the GCC node on MSM8226. Signed-off-by:
Rayyan Ansari <rayyan@ansari.sh> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230121192540.9177-3-rayyan@ansari.sh
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Christian Marangi authored
Change kpss-acc-v2 nodes naming to power-manager to reflect Documentation schema. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230116204751.23045-8-ansuelsmth@gmail.com
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Christian Marangi authored
Add missing clock configuration by adding clocks, clock-names, clock-output-names and #clock-cells bindings for each kpss-acc-v1 clock-controller to reflect Documentation schema. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230116204751.23045-7-ansuelsmth@gmail.com
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Christian Marangi authored
Add missing clock configuration by adding clocks, clock-names and #clock-cells bindings for each kpss-acc-v1 clock-controller node for apq8064 and msm8960 to reflect Documentation schema. Add missing #clock-cells binding and remove useless clock-output-names for ipq806x dtsi. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230116204751.23045-6-ansuelsmth@gmail.com
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Christian Marangi authored
Add per Soc compatible for qcom,kpss-gcc nodes. While currently not used by the kpss driver they can serve further customization and they are required to be defined per Documentation schema. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230116204751.23045-5-ansuelsmth@gmail.com
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Kathiravan T authored
Document the new ipq5332 SoC/board device tree bindings Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230307062232.4889-7-quic_kathirav@quicinc.com
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- 14 Mar, 2023 7 commits
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Konrad Dybcio authored
The opp-320000000 name is rather misleading with the opp-hz value of 450 MHz. Fix it! Fixes: 8db0b6c7 ("ARM: dts: qcom: apq8064: Convert adreno from legacy gpu-pwrlevels to opp-v2") Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
David Heidelberg <david@ixit.cz> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230220120831.1591820-1-konrad.dybcio@linaro.org
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Robert Marko authored
Now that sleep clock is being passed directly to GCC, there is no need for global name matching, so remove clk-output-names for sleep clock. Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230214162325.312057-4-robert.marko@sartura.hr
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Robert Marko authored
Directly pass XO and sleep clocks to GCC via phandles. Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230214162325.312057-3-robert.marko@sartura.hr
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Robert Marko authored
Since ath10k now supports loading the pre-cal via NVMEM instead of having to use userspace scripts, lets use it. Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230214161211.306462-4-robert.marko@sartura.hr
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Robert Marko authored
SPI-NAND node name should be flash@1 and not nand@1 according to schema. Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230214161211.306462-3-robert.marko@sartura.hr
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Robert Marko authored
Align USB power GPIO hog node to DT schema. Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230214161211.306462-2-robert.marko@sartura.hr
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Robert Marko authored
Add the required alias and stdout property so that kernel can setup the console based off DTS and not have to set it in the cmdline. Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230214161211.306462-1-robert.marko@sartura.hr
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- 13 Mar, 2023 1 commit
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Krzysztof Kozlowski authored
Add board compatible for QRD8550 - a mobile-like development board with SM8550. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230210163844.765074-1-krzysztof.kozlowski@linaro.org
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- 05 Mar, 2023 4 commits
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Linus Torvalds authored
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Linus Torvalds authored
Commit aa47a7c2 ("lib/cpumask: deprecate nr_cpumask_bits") resulted in the cpumask operations potentially becoming hugely less efficient, because suddenly the cpumask was always considered to be variable-sized. The optimization was then later added back in a limited form by commit 6f9c07be ("lib/cpumask: add FORCE_NR_CPUS config option"), but that FORCE_NR_CPUS option is not useful in a generic kernel and more of a special case for embedded situations with fixed hardware. Instead, just re-introduce the optimization, with some changes. Instead of depending on CPUMASK_OFFSTACK being false, and then always using the full constant cpumask width, this introduces three different cpumask "sizes": - the exact size (nr_cpumask_bits) remains identical to nr_cpu_ids. This is used for situations where we should use the exact size. - the "small" size (small_cpumask_bits) is the NR_CPUS constant if it fits in a single word and the bitmap operations thus end up able to trigger the "small_const_nbits()" optimizations. This is used for the operations that have optimized single-word cases that get inlined, notably the bit find and scanning functions. - the "large" size (large_cpumask_bits) is the NR_CPUS constant if it is an sufficiently small constant that makes simple "copy" and "clear" operations more efficient. This is arbitrarily set at four words or less. As a an example of this situation, without this fixed size optimization, cpumask_clear() will generate code like movl nr_cpu_ids(%rip), %edx addq $63, %rdx shrq $3, %rdx andl $-8, %edx callq memset@PLT on x86-64, because it would calculate the "exact" number of longwords that need to be cleared. In contrast, with this patch, using a MAX_CPU of 64 (which is quite a reasonable value to use), the above becomes a single movq $0,cpumask instruction instead, because instead of caring to figure out exactly how many CPU's the system has, it just knows that the cpumask will be a single word and can just clear it all. Note that this does end up tightening the rules a bit from the original version in another way: operations that set bits in the cpumask are now limited to the actual nr_cpu_ids limit, whereas we used to do the nr_cpumask_bits thing almost everywhere in the cpumask code. But if you just clear bits, or scan for bits, we can use the simpler compile-time constants. In the process, remove 'cpumask_complement()' and 'for_each_cpu_not()' which were not useful, and which fundamentally have to be limited to 'nr_cpu_ids'. Better remove them now than have somebody introduce use of them later. Of course, on x86-64 with MAXSMP there is no sane small compile-time constant for the cpumask sizes, and we end up using the actual CPU bits, and will generate the above kind of horrors regardless. Please don't use MAXSMP unless you really expect to have machines with thousands of cores. Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds authored
Pull crypto fix from Herbert Xu: "Fix a regression in the caam driver" * tag 'v6.3-p2' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: crypto: caam - Fix edesc/iv ordering mixup
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 updates from Thomas Gleixner: "A small set of updates for x86: - Return -EIO instead of success when the certificate buffer for SEV guests is not large enough - Allow STIPB to be enabled with legacy IBSR. Legacy IBRS is cleared on return to userspace for performance reasons, but the leaves user space vulnerable to cross-thread attacks which STIBP prevents. Update the documentation accordingly" * tag 'x86-urgent-2023-03-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: virt/sev-guest: Return -EIO if certificate buffer is not large enough Documentation/hw-vuln: Document the interaction between IBRS and STIBP x86/speculation: Allow enabling STIBP with legacy IBRS
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