- 09 Aug, 2021 6 commits
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Roy Chan authored
Acked-by:
Anson Jacob <Anson.Jacob@amd.com> Signed-off-by:
Roy Chan <roy.chan@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Roy Chan authored
Acked-by:
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Roy Chan authored
[Why] If the plane has been removed, the writeback disablement logic doesn't run [How] fix the logic order Acked-by:
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Eric Bernstein authored
Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Eric Bernstein <eric.bernstein@amd.com> Cc: stable@vger.kernel.org Tested-by:
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YuBiao Wang authored
When init failed in early init stage, amdgpu_object has not been initialized, so hasn't the ttm delayed queue functions. Signed-off-by:
YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by:
Emily.Deng <Emily.Deng@amd.com> Signed-off-by:
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Victor Zhao authored
- Extend wait time and add retry, currently 6s * 2times - Change timing algorithm Signed-off-by:
Victor Zhao <Victor.Zhao@amd.com> Signed-off-by:
Peng Ju Zhou <PengJu.Zhou@amd.com> Signed-off-by:
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- 06 Aug, 2021 34 commits
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Felix Kuehling authored
Currently the SVM get_attr call allows querying, which flags are set in the entire address range. Add the opposite query, which flags are clear in the entire address range. Both queries can be combined in a single get_attr call, which allows answering questions such as, "is this address range coherent, non-coherent, or a mix of both"? Proposed userspace for UAPI: https://github.com/RadeonOpenCompute/ROCR-Runtime/tree/memory_model_queriesSigned-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Philip Yand <philip.yang@amd.com> Signed-off-by:
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Colin Ian King authored
The variable eng_id is being initialized with a value that is never read, it is being re-assigned on the next statment. The assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Dan Carpenter authored
Check whether the kcalloc() fails and return -ENOMEM if it does. Fixes: 84ec374b ("drm/amdgpu: create amdgpu_vkms (v4)") Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Kenneth Feng authored
In some systems only MACO is supported. This is to fix the problem that runtime pm is enabled but BACO is not supported. MACO will be handled seperately. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
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Solomon Chiu authored
[Why] With kernel module parameter "freesync_video" is enabled, if the mode is changed to preferred mode(the mode with highest rate), then Freesync fails because the preferred mode is treated as one of freesync video mode, and then be configurated as freesync video mode(fixed refresh rate). [How] Skip freesync fixed rate configurating when modeset to preferred mode. Signed-off-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
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Christophe JAILLET authored
'watermarks_table' must be freed instead 'clocks_table', because 'clocks_table' is known to be NULL at this point and 'watermarks_table' is never freed if the last kzalloc fails. Fixes: c98ee897 ("drm/amd/pm: add the fine grain tuning function for vangogh") Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Sergio Miguéns Iglesias authored
Fixed braces, an unnecessary if statement and added a missing space. Reviewed-by:
Sergio Miguéns Iglesias <sergio@lony.xyz> Signed-off-by:
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Zhenneng Li authored
When primary bo is updated, crtc's pitch may have not been updated, this will lead to show disorder content when user changes display mode, we update crtc's pitch in page flip to avoid this bug. This refers to amdgpu's pageflip. v1->v2: Update all of the pitch in all of the page_flip functions in radeon rather than just the evergreen one. v2->v3: Update pitch set method for r100 according to radeon_legacy_crtc.c Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
Zhenneng Li <lizhenneng@kylinos.cn> Reviewed-by:
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Graham Sider authored
Add u32 gfx_target_version field to kfd_node_properties and kfd_device_info. Populate <asic>_device_info structs accordingly and expose to sysfs. This allows eliminating device-ID-based lookup tables in user mode for future ASICs. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
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Tuo Li authored
drm/amdgpu: drop redundant null-pointer checks in amdgpu_ttm_tt_populate() and amdgpu_ttm_tt_unpopulate() The varialbe gtt in the function amdgpu_ttm_tt_populate() and amdgpu_ttm_tt_unpopulate() is guaranteed to be not NULL in the context. Thus the null-pointer checks are redundant and can be dropped. Reported-by:
TOTE Robot <oslab@tsinghua.edu.cn> Reviewed-by:
Tuo Li <islituo@gmail.com> Signed-off-by:
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Alex Deucher authored
If the platform uses BOCO, don't use BACO in runtime suspend. We could end up executing the BACO path if the platform supports both. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1669Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Joseph Greathouse authored
Add the MODE register into the per-wave debug information. This register holds state such as FP rounding and denorm modes, which exceptions are enabled, and active clamping modes. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Acked-by:
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John Clements authored
update to latest atombios fw table Signed-off-by:
John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>. Signed-off-by:
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Peng Ju Zhou authored
The previous logic is recording the amount of valid vcn instances to use them on SRIOV, it is a hard task due to the vcn accessment is based on the index of the vcn instance. Check if the vcn instance enabled before do instance init. Signed-off-by:
Monk Liu <monk.liu@amd.com> Acked-by:
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John Clements authored
resolved race condition accessing psp cmd submission memory Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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John Clements authored
resolved bug with incorrect PSP BL cmd IDs Signed-off-by:
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Xiaomeng Hou authored
Update smu v13.0.1 firmware header for yellow carp. Signed-off-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Chengming Gui authored
Add device ids. Signed-off-by:
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Tom St Denis authored
Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Shirish S authored
DMUB firmware info is printed before it gets initialized. Correct this order to ensure true value is conveyed. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Aric Cyr authored
Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
To fully isolate FPU operations in a single place, we must avoid situations where compilers spill FP values to registers due to FP enable in a specific C file. Note that even if we isolate all FPU functions in a single file and call its interface from other files, the compiler might enable the use of FPU before we call DC_FP_START. Nevertheless, it is the programmer's responsibility to invoke DC_FP_START/END in the correct place. To highlight situations where developers forgot to use the FP protection before calling the DC FPU interface functions, we introduce a helper that checks if the function is invoked under FP protection. If not, it will trigger a kernel warning. Changes cince V3: - Rebase Changes cince V2 (Christian): - Do not use this_cpu_* between get/put_cpu_ptr(). - In the kernel documentation, better describe restrictions. - Make dc_assert_fp_enabled trigger the ASSERT message. Changes since V1: - Remove fp_enable variables - Rename dc_is_fp_enabled to dc_assert_fp_enabled - Replace wrong variable type Cc: Harry Wentland <harry.wentland@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Aric Cyr <aric.cyr@amd.com> Cc: Jun Lei <jun.lei@amd.com> Cc: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
DC invokes DC_FPU_START/END in multiple parts of the code; this can create a situation where we invoke this FPU operation in a nested way or exit too early. For avoiding this situation, this commit adds a mechanism where dc_fpu_begin/end manages the access to kernel_fpu_begin/end. Change since V3: - Rebase Change since V2: - Christian: Do not use this_cpu_* between get/put_cpu_ptr(). Change since V1: - Use a better variable names - Use get_cpu_ptr and put_cpu_ptr to better balance preemption enable and disable Cc: Harry Wentland <harry.wentland@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Aric Cyr <aric.cyr@amd.com> Cc: Jun Lei <jun.lei@amd.com> Cc: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Reported-by:
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Rodrigo Siqueira authored
DC invokes DC_FPU_START/END in multiple parts of the code; this can create a situation where we invoke this FPU operation in a nested way or exit too early. For avoiding this situation, this commit adds a mechanism where dc_fpu_begin/end manages the access to kernel_fpu_begin/end. Change since V3: - Christian: Move PPC64 code to dc_fpu_begin/end. Change since V2: - Christian: Do not use this_cpu_* between get/put_cpu_ptr(). Change since V1: - Use a better variable names - Use get_cpu_ptr and put_cpu_ptr to better balance preemption enable and disable Cc: Harry Wentland <harry.wentland@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Aric Cyr <aric.cyr@amd.com> Cc: Jun Lei <jun.lei@amd.com> Cc: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
The display core files rely on FPU, which requires to be compiled with special flags. Ideally, we don't want these FPU operations spread around the DC code; nevertheless, it happens in the current source. This commit introduces a new directory inside DML for centralizing shared DCN functions that require FPU and have been used outside DML. For illustrating this process of transferring FPU functions to the DML folder, this commit moves one of the functions dcn20_populate_dml_writeback_from_context) that require FPU access to a single shared file. Notice that this is the first part of the work, and it does not fix the FPU issue yet; we still need other patches for achieving the complete FPU isolation. Changes since V3: - Jun: Instead of creating a new directory to keep the FPU code, let's make the DML folder the only part that requires FPU access. Drop fpu_operation folder. - Christian: Fix function code style. Changes since V2: - Christian: Remove unnecessary wrapper. - lkp: Add missing prototype. - Only compile the FPU operations if the DCN option is enabled. Change since V1: - Update documentation and rebase. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Aric Cyr <aric.cyr@amd.com> Cc: Jun Lei <jun.lei@amd.com> Cc: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Reported-by:
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Qingqing Zhuo authored
[Why] HPD disable and enable sequences are not mutually exclusive on Linux. For HPDs that spans over 1s (i.e. HPD low = 1s), part of the disable sequence (specifically, a request to SMU to lower refclk) could come right before the call to PHY enable, causing DMUB to access an unresponsive PHY and thus a hard hang on the system. [How] Disable 48mhz refclk off on native DP. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Jaehyun Chung authored
[Why] We do not currently support ODM plus MPO on only one side of the screen. This unsupported case causes validation calculations to divide by zero due to invalid viewport values. [How] Add stopgap for the validation of ODM plus MPO on one side of screen case. Reviewed-by:
Jaehyun Chung <jaehyum.chung@amd.com> Signed-off-by:
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Jude Shih authored
[Why] On S4 resume we also need to fix detection of when to reload DMCUB firmware because we're currently using the VBIOS version which isn't compatible with the driver version. [How] Update the hardware init check for DCN31 since it's the ASIC that has this issue. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Jude Shih <jude.shih@amd.com> Signed-off-by:
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Roman Li authored
[Why] Display Manager initializes array of vblank workqueues, but only 1 is used. [How] Use single instance init instead of array. Reviewed-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Bing Guo authored
[Why&How] Hardware team suggested to use SRExitTime= 35.5us as w/a to prevent underflow in certain modes. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Bing Guo <bing.guo@amd.com> Signed-off-by:
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Bing Guo authored
Why: In DCN2x, HW doesn't automatically divide MASTER_UPDATE_LOCK_DB_X by the number of pipes ODM Combined. How: Set MASTER_UPDATE_LOCK_DB_X to the value that is adjusted by the number of pipes ODM Combined. Reviewed-by:
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Wesley Chalmers authored
[WHY] For DCN31 onward, LTTPR is to be enabled and set to Transparent by VBIOS. Driver is to assume that VBIOS has done this without needing to check the VBIOS interop bit. [HOW] Add LTTPR enable and interop VBIOS bits into dc->caps, and force-set the interop bit to true for DCN31+. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by:
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Candice Li authored
Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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