- 17 Feb, 2022 23 commits
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Yifan Zhang authored
Add below supports: GFX Coarse Grain Clock Gating(CGCG) GFX Coarse grain light sleep/deep sleep(CGLS) GFX Medium Grain Clock Gating(MGCG) GFX Medium Grain light sleep/deep sleep(MGLS) GFX Fine Grain Clock Gating(FGCG) RLC MGLS CP MGLS MMHUB Clock Gating SDMA Clock Gating HDP Clock Gating ATHUB Clock Gating IH Clock Gating GFX Power Gating Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Yifan Zhang authored
This patch adds add nv common init for gc 10.3.6. Signed-off-by:
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Alex Deucher authored
When we disable manual clock setting, we need to restore the cclks as well as the gfxclk. Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Tom Rix authored
Clang build fails with amdgpu_ras.c:2416:7: error: variable 'ras_obj' is used uninitialized whenever 'if' condition is true if (adev->in_suspend || amdgpu_in_reset(adev)) { ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ amdgpu_ras.c:2453:6: note: uninitialized use occurs here if (ras_obj->ras_cb) ^~~~~~~ There is a logic error in the error handler's labels. ex/ The sysfs: is the last goto label in the normal code but is the middle of error handler. Rework the error handler. cleanup: is the first error, so it's handler should be last. interrupt: is the second error, it's handler is next. interrupt: handles the failure of amdgpu_ras_interrupt_add_hander() by calling amdgpu_ras_interrupt_remove_handler(). This is wrong, remove() assumes the interrupt has been setup, not torn down by add(). Change the goto label to cleanup. sysfs is the last error, it's handler should be first. sysfs: handles the failure of amdgpu_ras_sysfs_create() by calling amdgpu_ras_sysfs_remove(). But when the create() fails there is nothing added so there is nothing to remove. This error handler is not needed. Remove the error handler and change goto label to interrupt. Fixes: b293e891 ("drm/amdgpu: add helper function to do common ras_late_init/fini (v3)") Reviewed-by:Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Luben Tuikov authored
Dynamically initialize IP instance attributes. This eliminates bugs stemming from adding new attributes to an IP instance. Cc: Alex Deucher <Alexander.Deucher@amd.com> Reported-by:
Tom StDenis <tom.stdenis@amd.com> Fixes: 4d7ba312 ("drm/amdgpu: Add "harvest" to IP discovery sysfs") Signed-off-by:
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Tom St Denis authored
Needed by umr to detect if ip discovered ASIC is an APU or not. (v2): Remove asic type from packet it's not strictly needed (v3): Correct comment Signed-off-by:
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Mario Limonciello authored
The `program_aspm` callback is already guarded for aspm, but the `enable_aspm` callback doesn't follow the module parameter. Update it to use the helper `amdgpu_device_should_use_aspm`. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Mario Limonciello authored
Evaluating `pcie_aspm_enabled` as part of driver probe has the implication that if one PCIe bridge with an AMD GPU connected doesn't support ASPM then none of them do. This is an invalid assumption as the PCIe core will configure ASPM for individual PCIe bridges. Create a new helper function that can be called by individual dGPUs to react to the `amdgpu_aspm` module parameter without having negative results for other dGPUs on the PCIe bus. Suggested-by:
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Luben Tuikov authored
Fix this ARM warning: drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:664:35: warning: format '%ld' expects argument of type 'long int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Wformat=] Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: kbuild-all@lists.01.org Cc: linux-kernel@vger.kernel.org Reported-by:kernel test robot <lkp@intel.com> Fixes: a6c40b17 ("drm/amdgpu: Show IP discovery in sysfs") Signed-off-by:
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Mario Limonciello authored
commit 0064b0ce ("drm/amd/pm: enable ASPM by default") enabled ASPM by default but a variety of hardware configurations it turns out that this caused a regression. * PPC64LE hardware does not support ASPM at a hardware level. CONFIG_PCIEASPM is often disabled on these architectures. * Some dGPUs on ALD platforms don't work with ASPM enabled and PCIe subsystem disables it Check with the PCIe subsystem to see that ASPM has been enabled or not. Fixes: 0064b0ce ("drm/amd/pm: enable ASPM by default") Link: https://wiki.raptorcs.com/w/images/a/ad/P9_PHB_version1.0_27July2018_pub.pdf Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1723 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1739 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1885 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1907 Tested-by: koba.ko@canonical.com Reviewed-by:
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yipechai authored
1. Define amdgpu_ras_block_late_init_default in amdgpu_ras.c as .ras_late_init common function, which is called when .ras_late_init of ras block isn't initialized. 2. Remove the code of using amdgpu_ras_block_late_init to initialize .ras_late_init in ras blocks. Signed-off-by:
yipechai <YiPeng.Chai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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yipechai authored
Define amdgpu_ras_late_init to call all ras blocks' .ras_late_init. Signed-off-by:
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yipechai authored
1. Move calling ras block instance members from module internal function to the top calling xxx_ras_late_init. 2. Module internal function calls can only use parameter variables of xxx_ras_late_init instead of ras block instance members. Signed-off-by:
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yipechai authored
Remove redundant calls of ras_late_init in mca ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of ras_late_init in mmhub ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of ras_late_init in hdp ras block. Signed-off-by:
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yipechai authored
Modify .ras_late_init function pointer parameter so that it can remove redundant intermediate calls in some ras blocks. Signed-off-by:
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Prike Liang authored
Add 3.1.6 DCE IP and assign relevant sw DM function for the new DCE. Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Hansen Dsouza authored
Add core DC implementation for DCN316. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by:
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Leo Li authored
Initialize DMUB for DCN316. Use same funcs as DCN31 for DCN316. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
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Prike Liang authored
- set DC version - add construct/destroy dc clock management function - register dcn interrupt handler Signed-off-by:
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Leo Li authored
Reviewed-by:
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Leo Li authored
Add register headers for the following IPs: - DCN 3.1.6 - DPCS 4.2.3 Acked-by:
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- 16 Feb, 2022 17 commits
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Prike Liang authored
Needed to properly initialize GC 10.3.7. Signed-off-by:
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Felix Kuehling authored
Reference: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays CC: Changcheng Deng <deng.changcheng@zte.com.cn> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Prike Liang authored
Initialize SDMA engine firmware loading. Signed-off-by:
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Prike Liang authored
Set smu sw function and enable swSMU support for MP1. Signed-off-by:
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Prike Liang authored
Set psp sw funcs callback and firmware loading for MP0. Signed-off-by:
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Prike Liang authored
Set gfxhub function and configure VM for GC block. Signed-off-by:
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Sathishkumar S authored
update vcn and jpeg power gating flags for VCN 3.1.1 Signed-off-by:
Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Prike Liang authored
Add new revision ID for GC 10.3.7 and set cg/pg flags. Signed-off-by:
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Prike Liang authored
Set nv_common_ip_block for GC 10.3.7. Signed-off-by:
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Prike Liang authored
Add SMUIO sw function for the new SMUIO block. Signed-off-by:
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Mario Limonciello authored
The message `Voltage value looks like a Leakage ID but it's not patched` shows up as an error on Dell Precision 3540. This doesn't cause functional problems and should be downgraded to info. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1162Reviewed-by:
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Prike Liang authored
add nbio sw func for the new 7.5.1 nbio block. Signed-off-by:
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Alex Deucher authored
Since this is an existing asic, adjust the code to follow the same logic as previously so the driver state is consistent. No functional change intended. Acked-by:
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Michel Dänzer authored
Even if PSR is allowed for a present GPU, there might be no eDP link which supports PSR. Fixes: 70897848 ("drm/amdgpu/display: Only set vblank_disable_immediate when PSR is not enabled") Reviewed-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Tao Zhou authored
Otherwise gpu reset will be triggered unconditionally in poison consumption. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Changcheng Deng authored
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use "flexible array members" for these cases. The older style of one-element or zero-length arrays should no longer be used. Reference: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arraysReported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Changcheng Deng <deng.changcheng@zte.com.cn> Acked-by:
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Roman Li authored
[Why] The previous change: "Add affected crtcs to atomic state for dsc mst unplug" forces modeset on all added crctc regardless whether timing changed or not. Per our implementation of dsc we need modeset only if timing changed. Otherwise dsc can be programmed incorrectly leading to dsc engine hang. [How] During atomic_check pre-compute dsc params. Only set mode_changed if timing is changed. Reviewed-by:
Hersen Wu <hersenwu@amd.com> Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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