1. 14 Jul, 2020 6 commits
    • Mark Brown's avatar
      Merge series "mtd: spi-nor: add xSPI Octal DTR support" from Pratyush Yadav <p.yadav@ti.com>: · 510a230b
      Mark Brown authored
      Hi,
      
      This series adds support for octal DTR flashes in the spi-nor framework,
      and then adds hooks for the Cypress Semper and Mircom Xcella flashes to
      allow running them in octal DTR mode. This series assumes that the flash
      is handed to the kernel in Legacy SPI mode.
      
      Tested on TI J721e EVM with 1-bit ECC on the Cypress flash.
      
      Changes in v10:
      - Rebase on latest linux-next/master. Drop a couple patches that made it
        in the  previous release.
      
      - Move the code that sets 20 dummy cycles for MT35XU512ABA to its octal
        enable function. This way, if the controller doesn't support 8D mode
        20 dummy cycles won't be used.
      
      Changes in v9:
      - Do not use '& 0xff' to get the opcode LSB in spi-mxic and
        spi-zynq-qspi. The cast to u8 will do that anyway.
      
      - Do not use if (opcode) as a check for whether the command phase exists
        in spi-zynq-qspi because the opcode 0 can be valid. Use the new
        cmd.nbytes instead.
      
      Changes in v8:
      - Move controller changes in spi-mxic to the commit which introduces
        2-byte opcodes to avoid problems when bisecting.
      
      - Replace usage of sizeof(op->cmd.opcode) with op->cmd.nbytes.
      
      - Extract opcode in spi-zynq-qspi instead of using &op->cmd.opcode.
      
      Changes in v7:
      - Reject ops with more than 1 command byte in
        spi_mem_default_supports_op().
      
      - Reject ops with more than 1 command byte in atmel and mtk controllers.
      
      - Reject ops with 0 command bytes in spi_mem_check_op().
      
      - Set cmd.nbytes to 1 when using SPI_MEM_OP_CMD().
      
      - Avoid endianness problems in spi-mxic.
      
      Changes in v6:
      - Instead of hard-coding 8D-8D-8D Fast Read dummy cycles to 20, find
        them out from the Profile 1.0 table.
      
      Changes in v5:
      - Do not enable stateful X-X-X modes if the reset line is broken.
      
      - Instead of setting SNOR_READ_HWCAPS_8_8_8_DTR from Profile 1.0 table
        parsing, do it in spi_nor_info_init_params() instead based on the
        SPI_NOR_OCTAL_DTR_READ flag instead.
      
      - Set SNOR_HWCAPS_PP_8_8_8_DTR in s28hs post_sfdp hook since this
        capability is no longer set in Profile 1.0 parsing.
      
      - Instead of just checking for spi_nor_get_protocol_width() in
        spi_nor_octal_dtr_enable(), make sure the protocol is
        SNOR_PROTO_8_8_8_DTR since get_protocol_width() only cares about data
        width.
      
      - Drop flag SPI_NOR_SOFT_RESET. Instead, discover soft reset capability
        via BFPT.
      
      - Do not make an invalid Quad Enable BFPT field a fatal error. Silently
        ignore it by assuming no quad enable bit is present.
      
      - Set dummy cycles for Cypress Semper flash to 24 instead of 20. This
        allows for 200MHz operation in 8D mode compared to the 166MHz with 20.
      
      - Rename spi_nor_cypress_octal_enable() to
        spi_nor_cypress_octal_dtr_enable().
      
      - Update spi-mtk-nor.c to reject DTR ops since it doesn't call
        spi_mem_default_supports_op().
      
      Changes in v4:
      - Refactor the series to use the new spi-nor framework with the
        manufacturer-specific bits separated from the core.
      
      - Add support for Micron MT35XU512ABA.
      
      - Use cmd.nbytes as the criteria of whether the data phase exists or not
        instead of cmd.buf.in || cmd.buf.out in spi_nor_spimem_setup_op().
      
      - Update Read FSR to use the same dummy cycles and address width as Read
        SR.
      
      - Fix BFPT parsing stopping too early for JESD216 rev B flashes.
      
      - Use 2 byte reads for Read SR and FSR commands in DTR mode.
      
      Changes in v3:
      - Drop the DT properties "spi-rx-dtr" and "spi-tx-dtr". Instead, if
        later a need is felt to disable DTR in case someone has a board with
        Octal DTR capable flash but does not support DTR transactions for some
        reason, a property like "spi-no-dtr" can be added.
      
      - Remove mode bits SPI_RX_DTR and SPI_TX_DTR.
      
      - Remove the Cadence Quadspi controller patch to un-block this series. I
        will submit it as a separate patch.
      
      - Rebase on latest 'master' and fix merge conflicts.
      
      - Update read and write dirmap templates to use DTR.
      
      - Rename 'is_dtr' to 'dtr'.
      
      - Make 'dtr' a bitfield.
      
      - Reject DTR ops in spi_mem_default_supports_op().
      
      - Update atmel-quadspi to reject DTR ops. All other controller drivers
        call spi_mem_default_supports_op() so they will automatically reject
        DTR ops.
      
      - Add support for both enabling and disabling DTR modes.
      
      - Perform a Software Reset on flashes that support it when shutting
        down.
      
      - Disable Octal DTR mode on suspend, and re-enable it on resume.
      
      - Drop enum 'spi_mem_cmd_ext' and make command opcode u16 instead.
        Update spi-nor to use the 2-byte command instead of the command
        extension. Since we still need a "extension type", mode that enum to
        spi-nor and name it 'spi_nor_cmd_ext'.
      
      - Default variable address width to 3 to fix SMPT parsing.
      
      - Drop non-volatile change to uniform sector mode and rely on parsing
        SMPT.
      
      Changes in v2:
      - Add DT properties "spi-rx-dtr" and "spi-tx-dtr" to allow expressing
        DTR capabilities.
      
      - Set the mode bits SPI_RX_DTR and SPI_TX_DTR when we discover the DT
        properties "spi-rx-dtr" and spi-tx-dtr".
      
      - spi_nor_cypress_octal_enable() was updating nor->params.read[] with
        the intention of setting the correct number of dummy cycles. But this
        function is called _after_ selecting the read so setting
        nor->params.read[] will have no effect. So, update nor->read_dummy
        directly.
      
      - Fix spi_nor_spimem_check_readop() and spi_nor_spimem_check_pp()
        passing nor->read_proto and nor->write_proto to
        spi_nor_spimem_setup_op() instead of read->proto and pp->proto
        respectively.
      
      - Move the call to cqspi_setup_opcode_ext() inside cqspi_enable_dtr().
        This avoids repeating the 'if (f_pdata->is_dtr)
        cqspi_setup_opcode_ext()...` snippet multiple times.
      
      - Call the default 'supports_op()' from cqspi_supports_mem_op(). This
        makes sure the buswidth requirements are also enforced along with the
        DTR requirements.
      
      - Drop the 'is_dtr' argument from spi_check_dtr_req(). We only call it
        when a phase is DTR so it is redundant.
      
      Pratyush Yadav (17):
        spi: spi-mem: allow specifying whether an op is DTR or not
        spi: spi-mem: allow specifying a command's extension
        spi: atmel-quadspi: reject DTR ops
        spi: spi-mtk-nor: reject DTR ops
        mtd: spi-nor: add support for DTR protocol
        mtd: spi-nor: sfdp: get command opcode extension type from BFPT
        mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table
        mtd: spi-nor: core: use dummy cycle and address width info from SFDP
        mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode
        mtd: spi-nor: core: enable octal DTR mode when possible
        mtd: spi-nor: sfdp: do not make invalid quad enable fatal
        mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT
        mtd: spi-nor: core: perform a Soft Reset on shutdown
        mtd: spi-nor: core: disable Octal DTR mode on suspend.
        mtd: spi-nor: core: expose spi_nor_default_setup() in core.h
        mtd: spi-nor: spansion: add support for Cypress Semper flash
        mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode
      
       drivers/mtd/spi-nor/core.c      | 446 +++++++++++++++++++++++++++-----
       drivers/mtd/spi-nor/core.h      |  22 ++
       drivers/mtd/spi-nor/micron-st.c | 103 +++++++-
       drivers/mtd/spi-nor/sfdp.c      | 131 +++++++++-
       drivers/mtd/spi-nor/sfdp.h      |   8 +
       drivers/mtd/spi-nor/spansion.c  | 166 ++++++++++++
       drivers/spi/atmel-quadspi.c     |   6 +
       drivers/spi/spi-mem.c           |  16 +-
       drivers/spi/spi-mtk-nor.c       |  10 +-
       drivers/spi/spi-mxic.c          |   3 +-
       drivers/spi/spi-zynq-qspi.c     |  11 +-
       include/linux/mtd/spi-nor.h     |  53 +++-
       include/linux/spi/spi-mem.h     |  14 +-
       13 files changed, 889 insertions(+), 100 deletions(-)
      
      --
      2.27.0
      
      base-commit: b3a9e3b9
      
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      510a230b
    • Linus Walleij's avatar
      spi: omap-100k: Drop include · 8257083f
      Linus Walleij authored
      The OMAP-100k driver includes <linux/gpio.h> but does not
      use any symbols from it, so drop the include.
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Link: https://lore.kernel.org/r/20200714073357.34879-1-linus.walleij@linaro.orgSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      8257083f
    • Pratyush Yadav's avatar
      spi: spi-mtk-nor: reject DTR ops · 4728f073
      Pratyush Yadav authored
      Double Transfer Rate (DTR) ops are added in spi-mem. But this controller
      doesn't support DTR transactions. Since we don't use the default
      supports_op(), which rejects all DTR ops, do that explicitly in our
      supports_op().
      Signed-off-by: default avatarPratyush Yadav <p.yadav@ti.com>
      Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
      Link: https://lore.kernel.org/r/20200623183030.26591-5-p.yadav@ti.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      4728f073
    • Pratyush Yadav's avatar
      spi: atmel-quadspi: reject DTR ops · 5c81c275
      Pratyush Yadav authored
      Double Transfer Rate (DTR) ops are added in spi-mem. But this controller
      doesn't support DTR transactions. Since we don't use the default
      supports_op(), which rejects all DTR ops, do that explicitly in our
      supports_op().
      Signed-off-by: default avatarPratyush Yadav <p.yadav@ti.com>
      Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
      Link: https://lore.kernel.org/r/20200623183030.26591-4-p.yadav@ti.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      5c81c275
    • Pratyush Yadav's avatar
      spi: spi-mem: allow specifying a command's extension · caf72df4
      Pratyush Yadav authored
      In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
      the "command extension". There can be 3 types of extensions in xSPI:
      repeat, invert, and hex. When the extension type is "repeat", the same
      opcode is sent twice. When it is "invert", the second byte is the
      inverse of the opcode. When it is "hex" an additional opcode byte based
      is sent with the command whose value can be anything.
      
      So, make opcode a 16-bit value and add a 'nbytes', similar to how
      multiple address widths are handled.
      
      Some places use sizeof(op->cmd.opcode). Replace them with op->cmd.nbytes
      
      The spi-mxic and spi-zynq-qspi drivers directly use op->cmd.opcode as a
      buffer. Now that opcode is a 2-byte field, this can result in different
      behaviour depending on if the machine is little endian or big endian.
      Extract the opcode in a local 1-byte variable and use that as the buffer
      instead. Both these drivers would reject multi-byte opcodes in their
      supports_op() hook anyway, so we only need to worry about single-byte
      opcodes for now.
      
      The above two changes are put in this commit to keep the series
      bisectable.
      Signed-off-by: default avatarPratyush Yadav <p.yadav@ti.com>
      Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
      Link: https://lore.kernel.org/r/20200623183030.26591-3-p.yadav@ti.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      caf72df4
    • Pratyush Yadav's avatar
      spi: spi-mem: allow specifying whether an op is DTR or not · 4c5e2bba
      Pratyush Yadav authored
      Each phase is given a separate 'dtr' field so mixed protocols like
      4S-4D-4D can be supported.
      Signed-off-by: default avatarPratyush Yadav <p.yadav@ti.com>
      Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
      Link: https://lore.kernel.org/r/20200623183030.26591-2-p.yadav@ti.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      4c5e2bba
  2. 13 Jul, 2020 1 commit
    • Linus Walleij's avatar
      spi: imx/fsl-lpspi: Convert to GPIO descriptors · 8cdcd8ae
      Linus Walleij authored
      This converts the two Freescale i.MX SPI drivers
      Freescale i.MX (CONFIG_SPI_IMX) and Freescale i.MX LPSPI
      (CONFIG_SPI_FSL_LPSPI) to use GPIO descriptors handled in
      the SPI core for GPIO chip selects whether defined in
      the device tree or a board file.
      
      The reason why both are converted at the same time is
      that they were both using the same platform data and
      platform device population helpers when using
      board files intertwining the code so this gives a cleaner
      cut.
      
      The platform device creation was passing a platform data
      container from each boardfile down to the driver using
      struct spi_imx_master from <linux/platform_data/spi-imx.h>,
      but this was only conveying the number of chipselects and
      an int * array of the chipselect GPIO numbers.
      
      The imx27 and imx31 platforms had code passing the
      now-unused platform data when creating the platform devices,
      this has been repurposed to pass around GPIO descriptor
      tables. The platform data struct that was just passing an
      array of integers and number of chip selects for the GPIO
      lines has been removed.
      
      The number of chipselects used to be passed from the board
      file, because this number also limits the number of native
      chipselects that the platform can use. To deal with this we
      just augment the i.MX (CONFIG_SPI_IMX) driver to support 3
      chipselects if the platform does not define "num-cs" as a
      device property (such as from the device tree). This covers
      all the legacy boards as these use <= 3 native chip selects
      (or GPIO lines, and in that case the number of chip selects
      is determined by the core from the number of available
      GPIO lines). Any new boards should use device tree, so
      this is a reasonable simplification to cover all old
      boards.
      
      The LPSPI driver never assigned the number of chipselects
      and thus always fall back to the core default of 1 chip
      select if no GPIOs are defined in the device tree.
      
      The Freescale i.MX driver was already partly utilizing
      the SPI core to obtain the GPIO numbers from the device tree,
      so this completes the transtion to let the core handle all
      of it.
      
      All board files and the core i.MX boardfile registration
      code is augmented to account for these changes.
      
      This has been compile-tested with the imx_v4_v5_defconfig
      and the imx_v6_v7_defconfig.
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Acked-by: default avatarShawn Guo <shawnguo@kernel.org>
      Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
      Cc: Robin Gong <yibin.gong@nxp.com>
      Cc: Trent Piepho <tpiepho@impinj.com>
      Cc: Clark Wang <xiaoning.wang@nxp.com>
      Cc: Shawn Guo <shawnguo@kernel.org>
      Cc: Sascha Hauer <s.hauer@pengutronix.de>
      Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
      Cc: Fabio Estevam <festevam@gmail.com>
      Cc: NXP Linux Team <linux-imx@nxp.com>
      Link: https://lore.kernel.org/r/20200625200252.207614-1-linus.walleij@linaro.orgSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      8cdcd8ae
  3. 10 Jul, 2020 3 commits
  4. 09 Jul, 2020 3 commits
  5. 07 Jul, 2020 13 commits
  6. 06 Jul, 2020 1 commit
  7. 01 Jul, 2020 13 commits