- 30 Dec, 2007 1 commit
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Paul Mackerras authored
This reverts commit 553aa765 at Ben H's request, because it confused IORESOURCE_* flags with command register bits. Requested-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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- 25 Dec, 2007 2 commits
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Josh Boyer authored
Update the 4xx board defconfigs Signed-off-by:Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
Remove some unneeded braces and make a busy loop more obvious. Signed-off-by:
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- 24 Dec, 2007 4 commits
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Josh Boyer authored
Some machine_xx_initcall macros were recently added that check for the machine type before calling the function. This converts the 4xx platforms to use those for bus probing. Signed-off-by: -
Josh Boyer authored
Remove the declarations for isa_io_base and isa_mem_base as they are declared in pci-common.c now. Signed-off-by: -
Josh Boyer authored
The e200 and e500 platforms are separated in various parts of the kernel with ifdefs, most notably reg_booke.h and traps.c. The new machine_check rework requires them to be similarly separated in cputable.c to avoid compile errors. Signed-off-by: -
Josh Boyer authored
Mark the of_device_id structures used to probe the various busses on 4xx as __initdata. Signed-off-by:
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- 23 Dec, 2007 33 commits
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Josh Boyer authored
Enable PCI support for these eval boards among other things. Also selects PCI for Rainier in the Kconfig file. Signed-off-by: -
Stefan Roese authored
Signed-off-by:
Stefan Roese <sr@denx.de> Signed-off-by:
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Stefan Roese authored
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Stefan Roese authored
This patch adds basic support for the AMCC Makalu board to arch/powerpc. Signed-off-by:
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Stefan Roese authored
Currently we have some limitations in the 4xx PCIe driver and can't support all possible PCIe busses. But the current limits in the dts file are quite low (only 16 busses per RC). This patch increases the number to 64 per RC. Signed-off-by:
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Stefan Roese authored
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Valentine Barshak authored
This adds PCI entry to PowerPC 440GRx Rainier DTS. Signed-off-by:
Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by:
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Valentine Barshak authored
Renaming the CPU nodes with generic names put the CPU model in the "model" property and thus broke the PowerPC 440EP(x)/440GR(x) identical PVR workaround. The updates it to use the new model property for CPU identification. Signed-off-by:
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Josh Boyer authored
Recent DTC versions disallow certain special characters in full paths without being quoted with {}. That however breaks compatibility with older DTC versions. Work around this by renaming the CPU nodes for the 4xx files to a generic node name, and specify the processor type in the model property of the CPU node. Signed-off-by: -
Stefan Roese authored
This patch sets the ibpre flag (Inbound Presence) for the 405EX in the 4xx PCIe driver. Signed-off-by:
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Stefan Roese authored
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Stefan Roese authored
The recent changes from Benjamin Herrenschmidt to the ibm_newemac now make it possible to support other 4xx variants by just defining the correct properties in the device tree. In this case of the 405EX we need to define "has-mdio" in the RGMII node and "has-inverted-stacr-oc" and "has-new-stacr-staopc" in the EMAC node same as on the 440EPx. Signed-off-by:
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Stefan Roese authored
For EMAC support, 405EX needs to be defined to enable the corresponding EMAC features (IBM_NEW_EMAC_EMAC4, etc.). Signed-off-by:
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Stefan Roese authored
Right now TLB entry 0 ist used as UART0 mapping for the early debug output (via CONFIG_SERIAL_TEXT_DEBUG). This causes problems when many TLB's get used upon Linux bootup (e.g. while PCIe scanning behind bridges and/or switches on 440SPe platforms). This will overwrite the TLB 0 entry and further debug output's may crash/hang the system. This patch moves the early debug UART0 TLB entry from 0 to 62 as done in arch/powerpc. This way it is in the "pinned" area and will not get overwritten. Also the arch/ppc/mm/44x_mmu.c code is now synced with the newer code from arch/powerpc. Signed-off-by:
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Josh Boyer authored
Update the Rainier wrapper for the libfdt merge and add the pci flags to the platform file. Signed-off-by: -
Josh Boyer authored
A small error caused a header file to be removed making sequoia support no longer compile. Fix it. Signed-off-by: -
Valentine Barshak authored
PowerPC 440Epx/GRx Sequoia/Rainier updates for 2.6.25 Signed-off-by:
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Josh Boyer authored
The mechanism to do the setup for 440A cores changed recently. This fixes the 440grx setup function to call __fixup_440A_mcheck. Signed-off-by: -
Valentine Barshak authored
This adds PCI entry to PowerPC 440EPx Sequoia DTS. Signed-off-by:
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Valentine Barshak authored
Correct the PowerPC 440GRx machine check callback. Signed-off-by:
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Valentine Barshak authored
This is a UIC cascade handler rework to use set_irq_chained_handler() for cascade, just like othe ppc platforms do. With current implementation we have additional redirection for irq handler and we call generic_handle_irq twice (once for the primary uic and the other time for handling cascade interrupt). This causes Ingo's realtime support patch to stop working on 4xx. Not sure of any other possible problems though, but with set_irq_chained_handler() we can abolish "struct irqaction cascade" from the chip descriptor and call generic_handle_irq() once, directly for cascade irq. Signed-off-by:
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Valentine Barshak authored
This patch makes PowerPC 4xx UIC use generic level irq handler instead of a custom handle_uic_irq() function. We ack only edge irqs in mask_ack callback, since acking a level irq on UIC has no effect if the interrupt is still asserted by the device, even if the interrupt is already masked. So, to really de-assert the interrupt we need to de-assert the external source first *and* ack it on UIC then. The handle_level_irq() function masks and ack's the interrupt with mask_ack callback prior to calling the actual ISR and unmasks it at the end. So, to use it with UIC interrupts we need to ack level irqs in the unmask callback instead, after the ISR has de-asserted the external interrupt source. Even if we ack the interrupt that we didn't handle (unmask/ack it at the end of the handler, while next irq is already pending) it will not de-assert the irq, untill we de-assert its exteral source. Signed-off-by:
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Valentine Barshak authored
PowerPC 440GRx Rainier default config. Signed-off-by:
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Valentine Barshak authored
PowerPC 440GRx Rainier board support. Signed-off-by:
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Valentine Barshak authored
PowerPC 440GRx Rainier DTS. Signed-off-by:
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Valentine Barshak authored
Bootwrapper code for PowerPC 440GRx Rainier board. Signed-off-by:
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Valentine Barshak authored
Add the 440EPx Sequoia USB OHCI device tree entry. Signed-off-by:
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Stefan Roese authored
This patch adds runtime detection of the 440SPe revision A chips. These chips are equipped with a slighly different PCIe core and need special/ different initialization. The compatible node is changed to "plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that can be equipped with both PPC revisions like the AMCC Yucca. Signed-off-by: -
Benjamin Herrenschmidt authored
This makes 4xx embedded platforms re-assign all PCI resources as we pretty much never care about what the various firmwares have done on these, it's generally not compatible with the way the kernel will map the bridges. We still need to also enable bus renumbering on some of them, but I will do that from a separate patch after I've fixed 4xx PCIe to handle all bus numbers. Signed-off-by:
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Benjamin Herrenschmidt authored
This improves the way the 4xx PCI-E code handles checking for a link and adds explicit testing of CRS result codes on config space accesses. This should make it more reliable. Also, bridges with no link are now still created, though config space accesses beyond the root complex are filtered. This is one step toward eventually supporting hotplug. Signed-off-by:
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Benjamin Herrenschmidt authored
This removes a bogus empty "ranges" property in the EBC device node of the Bamboo board device-tree. The "ranges" property should be created by the wrapper code when it is implemented. Until then, remove the empty property since it incorrectly implies that there is a 1:1 address mapping between the EBC and the OPB. This also fixes a warning from newer DTCs. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds base support for the Katmai board, including PCI-X and PCI-Express (but no RTC, nvram, etc... yet). Signed-off-by:
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Benjamin Herrenschmidt authored
This reworks the boot wrapper library function that probes the chip clocks. Better separate the base function that is used on 440GX,SPe,EP,... from the uart fixups as those need different device-tree path on different processors. Also, rework the function itself based on the arch/ppc code from Eugene Surovegin which I find more readable, and which handles one more bypass case. Also handle the subtle difference between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived from the PLB clock while on the later, it's derived from the OPB. Signed-off-by:
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