- 03 Feb, 2022 40 commits
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Jedrzej Jagielski authored
There was a race condition in access to hw->aq.asq_last_status while adding and deleting MAC/VLAN filters causing incorrect error status to be printed as ERROR OK instead of the correct error. Change calls to i40e_aq_add_macvlan in i40e_aqc_add_filters and i40e_aq_remove_macvlan in i40e_aqc_del_filters to _v2 versions that return Admin Queue status on the stack to avoid race conditions in access to hw->aq.asq_last_status. Signed-off-by:
Sylwester Dziedziuch <sylwesterx.dziedziuch@intel.com> Signed-off-by:
Jedrzej Jagielski <jedrzej.jagielski@intel.com> Tested-by:
Gurucharan G <gurucharanx.g@intel.com> Signed-off-by:
Tony Nguyen <anthony.l.nguyen@intel.com>
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Jedrzej Jagielski authored
ASQ send command functions are returning only i40e status codes yet some calling functions also need Admin Queue status that is stored in hw->aq.asq_last_status. Since hw object is stored on a heap it introduces a possibility for a race condition in access to hw if calling function is not fast enough to read hw->aq.asq_last_status before next send ASQ command is executed. Add new _v2 version of i40e_aq_add_macvlan that is using new _v2 versions of ASQ send command functions and returns the Admin Queue status on the stack. Signed-off-by:
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Jedrzej Jagielski authored
ASQ send command functions are returning only i40e status codes yet some calling functions also need Admin Queue status that is stored in hw->aq.asq_last_status. Since hw object is stored on a heap it introduces a possibility for a race condition in access to hw if calling function is not fast enough to read hw->aq.asq_last_status before next send ASQ command is executed. Add new versions of send ASQ command functions that return Admin Queue status on the stack to avoid race conditions in access to hw->aq.asq_last_status. Add new _v2 version of i40e_aq_remove_macvlan that is using new _v2 versions of ASQ send command functions and returns the Admin Queue status on the stack. Signed-off-by:
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Jedrzej Jagielski authored
Change functions: - i40e_aq_add_macvlan - i40e_aq_remove_macvlan - i40e_aq_delete_element - i40e_aq_add_vsi - i40e_aq_update_vsi_params to explicitly use i40e_asq_send_command_atomic(..., true) instead of i40e_asq_send_command, as they use mutexes and do some work in an atomic context. Without this change setting vlan via netdev will fail with call trace cased by bug "BUG: scheduling while atomic". Signed-off-by:
Witold Fijalkowski <witoldx.fijalkowski@intel.com> Signed-off-by:
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Jakub Kicinski authored
It's not used. Signed-off-by:
Jakub Kicinski <kuba@kernel.org> Reviewed-by:
Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by:
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Joe Damato authored
After commit 1a557afc ("i40e: Refactor receive routine"), rx_stats.realloc_count is no longer being incremented, so remove it. The debugfs string was left, but hardcoded to 0. This is intended to prevent breaking any existing code / scripts that are parsing debugfs for i40e. Signed-off-by:
Joe Damato <jdamato@fastly.com> Reviewed-by:
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Mateusz Palczewski authored
After loading driver hw-tc-offload is enabled by default. Change the behaviour of driver to disable hw-tc-offload by default as this is the expected state. Additionally since this impacts ntuple feature state change the way of checking NETIF_F_HW_TC flag. Signed-off-by:
Norbert Zulinski <norbertx.zulinski@intel.com> Signed-off-by:
Przemyslaw Patynowski <przemyslawx.patynowski@intel.com> Signed-off-by:
Mateusz Palczewski <mateusz.palczewski@intel.com> Tested-by:
Dave Switzer <david.switzer@intel.com> Signed-off-by:
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David S. Miller authored
Russell King says: ==================== net: dsa: mv88e6xxx: convert to phylink_generic_validate() The overall objective of this series is to convert the mv88e6xxx DSA driver to use phylink_generic_validate(). Patch 1 adds a new helper mv88e6352_g2_scratch_port_has_serdes() which indicates whether an 88e6352 port has a serdes associated with it. This is necessary as ports 4 and 5 will normally be in automedia mode, where the CMODE field in the port status register will change e.g. between 15 (internal PHY) and 9 (1000base-X) depending on whether the serdes has link. The existing code caches the cmode field, and depending whether the serdes has link at probe time, determines whether we allow things such as the serdes statistics to be accessed. This means if the link isn't up at probe time, the serdes is essentially unavailable. Patch 1 addresses this by reading the pin configuration to find out whether the serdes is attached to port 4 or port 5. Patch 2 is a joint effort between myself and Marek Behún, adding the supported interfaces and MAC capabilities to all mv88e6xxx supported switch devices. This is slightly more restrictive than the original code as we didn't used to care too much about the interface mode, but with this we do - which is why we must know if there's a serdes associated now. Patch 3 switches mv88e6xxx to use the generic validation by removing the initialisation of the phylink_validate pointer in the dsa_ops struct. Patch 4 updates the statistics code to use the new helper in patch 1, so the serdes statistics are available even if the link was down at driver probe time. ==================== Signed-off-by:David S. Miller <davem@davemloft.net>
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Russell King (Oracle) authored
The decision whether to report serdes statistics currently depends on the cached C_Mode value for the port, read at probe time or updated by configuration. However, port 4 can be in "automedia" mode when it is used as a serdes port, meaning it switches between the internal PHY and the serdes, changing the read-only C_Mode value depending on which first gains link. Consequently, the C_Mode value read at probe does not accurately reflect whether the port has the serdes associated with it. In "net: dsa: mv88e6xxx: add mv88e6352_g2_scratch_port_has_serdes()", we added a way to read the hardware configuration to determine which port has the serdes associated with it. Use this to determine which port reports the serdes statistics. Reviewed-by:
Marek Behún <kabel@kernel.org> Signed-off-by:
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Russell King (Oracle) authored
Now that the mv88e6xxx chip drivers are supplying the supported interfaces and MAC capabilities, switch the driver to use the generic phylink validation implementation by removing our own validation implementations. This causes DSA to call phylink_generic_validate() on our behalf. Reviewed-by:
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Russell King (Oracle) authored
Populate the supported interfaces and MAC capabilities for the Marvell MV88E6xxx DSA switches in preparation to using these for the validation functionality. Patch co-authored by Marek. Signed-off-by:
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Russell King (Oracle) authored
Read the hardware configuration to determine which port is attached to the serdes. Signed-off-by:
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David S. Miller authored
Tobias Waldekranz says: ==================== net: dsa: mv88e6xxx: Improve standalone port isolation The ideal isolation between standalone ports satisfies two properties: 1. Packets from one standalone port must not be forwarded to any other port. 2. Packets from a standalone port must be sent to the CPU port. mv88e6xxx solves (1) by isolating standalone ports using the PVT. Up to this point though, (2) has not guaranteed; as the ATU is still consulted, there is a chance that incoming packets never reach the CPU if its DA has previously been used as the SA of an earlier packet (see 1/5 for more details). This is typically not a problem, except for one very useful setup in which switch ports are looped in order to run the bridge kselftests in tools/testing/selftests/net/forwarding. This series attempts to solve (2). Ideally, we could simply use the "ForceMap" bit of more modern chips (Agate and newer) to classify all incoming packets as MGMT. This is not available on older silicon that is still widely used (Opal Plus chips like the 6097 for example). Instead, this series takes a two pronged approach: 1/5: Always clear MapDA on standalone ports to make sure that no ATU entry can lead packets astray. This solves (2) for single-chip systems. 2/5: Trivial prep work for 4/5. 3/5: Trivial prep work for 4/5. 4/5: On multi-chip systems though, this is not enough. On the incoming chip, the packet will be forced out towards the CPU thanks to 1/5, but on any intermediate chips the ATU is still consulted. We override this behavior by marking the reserved standalone VID (0) as a policy VID, the DSA ports' VID policy is set to TRAP. This will cause the packet to be reclassified as MGMT on the first intermediate chip, after which it's a straight shot towards the CPU. Finally, we allow more tests to be run on mv88e6xxx: 5/5: The bridge_vlan{,un}aware suites sets an ageing_time of 10s on the bridge it creates, but mv88e6xxx has a minimum supported time of 15s. Allow this time to be overridden in forwarding.config. With this series in place, mv88e6xxx passes the following kselftest suites: - bridge_port_isolation.sh - bridge_sticky_fdb.sh - bridge_vlan_aware.sh - bridge_vlan_unaware.sh v1 -> v2: - Wording/spelling (Vladimir) - Use standard iterator in dsa_switch_upstream_port (Vladimir) - Limit enabling of VTU port policy to downstream DSA ports (Vladimir) ==================== Signed-off-by: -
Tobias Waldekranz authored
Allow the ageing timeout that is set on bridges to be customized from forwarding.config. This allows the tests to be run on hardware which does not support a 10s timeout (e.g. mv88e6xxx). Signed-off-by:
Tobias Waldekranz <tobias@waldekranz.com> Reviewed-by:
Petr Machata <petrm@nvidia.com> Signed-off-by:
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Tobias Waldekranz authored
Given that standalone ports are now configured to bypass the ATU and forward all frames towards the upstream port, extend the ATU bypass to multichip systems. Load VID 0 (standalone) into the VTU with the policy bit set. Since VID 4095 (bridged) is already loaded, we now know that all VIDs in use are always available in all VTUs. Therefore, we can safely enable 802.1Q on DSA ports. Setting the DSA ports' VTU policy to TRAP means that all incoming frames on VID 0 will be classified as MGMT - as a result, the ATU is bypassed on all subsequent switches. With this isolation in place, we are able to support configurations that are simultaneously very quirky and very useful. Quirky because it involves looping cables between local switchports like in this example: CPU | .------. .---0---. | .----0----. | sw0 | | | sw1 | '-1-2-3-' | '-1-2-3-4-' $ @ '---' $ @ % % We have three physically looped pairs ($, @, and %). This is very useful because it allows us to run the kernel's kselftests for the bridge on mv88e6xxx hardware. Signed-off-by:Vladimir Oltean <olteanv@gmail.com> Signed-off-by:
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Tobias Waldekranz authored
This chip has support for the same per-port policy actions found in later versions of LinkStreet devices. Fixes: f3a2cd32 ("net: dsa: mv88e6xxx: introduce .port_set_policy") Signed-off-by:
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Tobias Waldekranz authored
A VTU entry with policy enabled is used in combination with a port's VTU policy setting to override normal switching behavior for frames assigned to the entry's VID. A typical example is to Treat all frames in a particular VLAN as control traffic, and trap them to the CPU. In which case the relevant user port's VTU policy would be set to TRAP. Signed-off-by:
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Tobias Waldekranz authored
Clear MapDA on standalone ports to bypass any ATU lookup that might point the packet in the wrong direction. This means that all packets are flooded using the PVT config. So make sure that standalone ports are only allowed to communicate with the local upstream port. Here is a scenario in which this is needed: CPU | .----. .---0---. | .--0--. | sw0 | | | sw1 | '-1-2-3-' | '-1-2-' '---' - sw0p1 and sw1p1 are bridged - sw0p2 and sw1p2 are in standalone mode - Learning must be enabled on sw0p3 in order for hardware forwarding to work properly between bridged ports 1. A packet with SA :aa comes in on sw1p2 1a. Egresses sw1p0 1b. Ingresses sw0p3, ATU adds an entry for :aa towards port 3 1c. Egresses sw0p0 2. A packet with DA :aa comes in on sw0p2 2a. If an ATU lookup is done at this point, the packet will be incorrectly forwarded towards sw0p3. With this change in place, the ATU is bypassed and the packet is forwarded in accordance with the PVT, which only contains the CPU port. Signed-off-by: -
David S. Miller authored
Miroslav Lichvar says: ==================== Virtual PTP clock improvements and fix v2: - dropped patch changing initial time of virtual clocks The first patch fixes an oops when unloading a driver with PTP clock and enabled virtual clocks. The other patches add missing features to make synchronization with virtual clocks work as well as with the physical clock. ==================== Signed-off-by: -
Miroslav Lichvar authored
If the physical clock supports cross timestamping (it has the getcrosststamp() function), provide a wrapper in the virtual clock to enable cross timestamping. This adds support for the PTP_SYS_OFFSET_PRECISE ioctl. Signed-off-by:
Miroslav Lichvar <mlichvar@redhat.com> Acked-by:
Richard Cochran <richardcochran@gmail.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by:
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Miroslav Lichvar authored
If the physical clock has the gettimex64() function, provide a gettimex64() wrapper in the virtual clock to enable more accurate and stable synchronization. This adds support for the PTP_SYS_OFFSET_EXTENDED ioctl. Signed-off-by:
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Miroslav Lichvar authored
Increase the maximum frequency offset of virtual clocks to 50% to enable faster slewing corrections. This value cannot be represented as scaled ppm when long has 32 bits, but that is already the case for other drivers, even those that provide the adjfine() function, i.e. 32-bit applications are expected to check for the limit. Signed-off-by:
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Miroslav Lichvar authored
When unregistering a physical clock which has some virtual clocks, unregister the virtual clocks with it. This fixes the following oops, which can be triggered by unloading a driver providing a PTP clock when it has enabled virtual clocks: BUG: unable to handle page fault for address: ffffffffc04fc4d8 Oops: 0000 [#1] PREEMPT SMP NOPTI RIP: 0010:ptp_vclock_read+0x31/0xb0 Call Trace: timecounter_read+0xf/0x50 ptp_vclock_refresh+0x2c/0x50 ? ptp_clock_release+0x40/0x40 ptp_aux_kworker+0x17/0x30 kthread_worker_fn+0x9b/0x240 ? kthread_should_park+0x30/0x30 kthread+0xe2/0x110 ? kthread_complete_and_exit+0x20/0x20 ret_from_fork+0x22/0x30 Fixes: 73f37068 ("ptp: support ptp physical/virtual clocks conversion") Signed-off-by:
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Alexander Duyck authored
This change is meant to permit a driver to perform "fragmenting" of the page from within the driver instead of the current model which requires pre-partitioning the page. The main motivation behind this is to support use cases where the page will be split up by the driver after DMA instead of before. With this change it becomes possible to start using page pool to replace some of the existing use cases where multiple references were being used for a single page, but the number needed was unknown as the size could be dynamic. For example, with this code it would be possible to do something like the following to handle allocation: page = page_pool_alloc_pages(); if (!page) return NULL; page_pool_fragment_page(page, DRIVER_PAGECNT_BIAS_MAX); rx_buf->page = page; rx_buf->pagecnt_bias = DRIVER_PAGECNT_BIAS_MAX; Then we would process a received buffer by handling it with: rx_buf->pagecnt_bias--; Once the page has been fully consumed we could then flush the remaining instances with: if (page_pool_defrag_page(page, rx_buf->pagecnt_bias)) continue; page_pool_put_defragged_page(pool, page -1, !!budget); The general idea is that we want to have the ability to allocate a page with excess fragment count and then trim off the unneeded fragments. Signed-off-by:Alexander Duyck <alexanderduyck@fb.com> Reviewed-by:
Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by:
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David S. Miller authored
Russell King says: ==================== Trivial DSA conversions to phylink_generic_validate() This series converts five DSA drivers to use phylink_generic_validate(). No feedback or testing reports were received from the CFT posting. ==================== Signed-off-by: -
Russell King (Oracle) authored
Populate the supported interfaces and MAC capabilities for the xrs700x family of DSA switches and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. According to commit ee00b24f ("net: dsa: add Arrow SpeedChips XRS700x driver") the switch supports one RMII port and up to three RGMII ports. This commit assumes that port 0 is the RMII port and the remainder are RGMII. This commit also results in the Autoneg bit being set in the ethtool link modes, which wasn't in the original; if this switch supports RGMII to a 10/100/1G PHY, then surely we want to allow Autoneg on the PHY. Signed-off-by:
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Russell King (Oracle) authored
Populate the supported interfaces and MAC capabilities for the QCA8K DSA switch and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. In making this change, we bring consistency to the ethtool linkmodes that phylink's validate step produces, thereby following the expected behaviour as the phylink documentation has explained. Specifically, the ethtool 1000baseX_Full capability is now permitted for all interface modes, as it is a property of the PHY driver whether 1000baseX fiber connections can be supported. Signed-off-by:
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Russell King (Oracle) authored
Populate the supported interfaces and MAC capabilities for the Microchip KSZ8795 DSA switch and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. Signed-off-by:
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Russell King (Oracle) authored
Populate the supported interfaces and MAC capabilities for the bcm_sf2 DSA switch and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. The exclusion of Gigabit linkmodes for MII and Reverse MII links is handled within phylink_generic_validate() in phylink, so there is no need to make them conditional on the interface mode in the driver. Thanks to Florian Fainelli for suggesting how to populate the supported interfaces. Link: https://lore.kernel.org/r/3b3fed98-0c82-99e9-dc72-09fe01c2bcf3@gmail.comSigned-off-by:
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Russell King (Oracle) authored
Populate the supported interfaces and MAC capabilities for the AR9331 DSA switch and remove the old validate implementation to allow DSA to use phylink_generic_validate() for this switch driver. Signed-off-by:
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David S. Miller authored
Mat Martineau says: ==================== mptcp: Miscellaneous changes for 5.18 Patch 1 has some minor cleanup in mptcp_write_options(). Patch 2 moves a rarely-needed branch to optimize mptcp_write_options(). Patch 3 adds a comment explaining which combinations of MPTCP option headers are expected. Patch 4 adds a pr_debug() for the MPTCP_RST option. Patches 5-7 allow setting MPTCP_PM_ADDR_FLAG_FULLMESH with the "set flags" netlink command. This allows changing the behavior of existing path manager endpoints. The flag was previously only set at endpoint creation time. Associated selftests also updated. ==================== Signed-off-by: -
Geliang Tang authored
This patch added the fullmesh setting and clearing selftests in mptcp_join.sh. Now we can set both backup and fullmesh flags, so avoid using the words 'backup' and 'bkup'. Acked-by:
Paolo Abeni <pabeni@redhat.com> Signed-off-by:
Geliang Tang <geliang.tang@suse.com> Signed-off-by:
Mat Martineau <mathew.j.martineau@linux.intel.com> Signed-off-by:
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Geliang Tang authored
This patch added the fullmesh flag setting and clearing support in pm_nl_ctl: # pm_nl_ctl set ip flags fullmesh # pm_nl_ctl set ip flags nofullmesh Acked-by:
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Geliang Tang authored
This patch added the fullmesh flag setting support in pm_netlink. If the fullmesh flag of the address is changed, remove all the related subflows, update the fullmesh flag and create subflows again. Acked-by:
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Geliang Tang authored
This patch printed out the reset infos, reset_transient and reset_reason, of MP_RST in mptcp_parse_option() to show that MP_RST is received. Signed-off-by:
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Matthieu Baerts authored
RFC8684 doesn't seem to clearly specify which MPTCP options can be used together. Some options are mutually exclusive -- e.g. MP_CAPABLE and MP_JOIN --, some can be used together -- e.g. DSS + MP_PRIO --, some can but we prefer not to -- e.g. DSS + ADD_ADDR -- and some have to be used together at some points -- e.g. MP_FAIL and DSS. We need to clarify this as a base before allowing other modifications. For example, does it make sense to send a RM_ADDR with an MPC or MPJ? This remains open for possible future discussions. Signed-off-by:
Matthieu Baerts <matthieu.baerts@tessares.net> Signed-off-by:
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Matthieu Baerts authored
MP_FAIL should be use in very rare cases, either when the TCP RST flag is set -- with or without an MP_RST -- or with a DSS, see mptcp_established_options(). Here, we do the same in mptcp_write_options(). Co-developed-by:
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Geliang Tang authored
Move the declarations of ssk and subflow in MP_FAIL and MP_PRIO to the beginning of the function mptcp_write_options(). Signed-off-by:
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Jakub Kicinski authored
Alex Elder says: ==================== net: ipa: support variable RX buffer size Specify the size of receive buffers used for RX endpoints in the configuration data, rather than using 8192 bytes for all of them. Increase the size of the AP receive buffer for the modem to 32KB. ==================== Link: https://lore.kernel.org/r/20220201153737.601149-1-elder@linaro.orgSigned-off-by:
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Alex Elder authored
Increase the receive buffer size used for data received from the modem to 32KB, to improve download performance by allowing much greater aggregation. Signed-off-by:
Alex Elder <elder@linaro.org> Signed-off-by:
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