- 19 Nov, 2019 40 commits
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Bhawanpreet Lakha authored
[Why] HDCP 2.2 uses type0 and type1 content type. This is passed to the receiver to stream the proper content. For example, in a MST case if the main device is HDCP2.2 capable but the secondary device is only 1.4 capabale we can use Type0 Type0 content: use HDCP 1.4 or HDCP2.2 type0 Type1 content: Only use HDCP 2.2 type1 [How] We use the "hdcp content type" property in drm. We use the disable_type1 flag in hdcp module to select the type based on the properties. For updating the property we use the same logic as 1.4, but now we consider content_type as well and update the property if the requirements are met Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Bhawanpreet Lakha authored
[Why] HDCP 2.2 was disabled, we need to enable it [How] -Update display topology to support 2.2 -Unset hdcp2.disable in update_config -Change logic of event_update_property, now we set the property to be ENABLED for any level of encryption (2.2 or 1.4). Signed-off-by:
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Bhawanpreet Lakha authored
[Why] HDCP is a bit finicky so we try it 3 times, this leads to a case where if we fail the first time and pass the second time the error is still shown in dmesg for the first failed attempt. This leads to false positive errors. [How] Change the logging from ERROR to WARNING. Warnings are still shown in dmesg to know what went wrong. Signed-off-by:
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Bhawanpreet Lakha authored
[Why] We need to log the state changes for 2.2 This patch extends the existing logging functions to handle HDCP2.2. [How] We do this by adding if/else in the defines, and output the log based on the hdcp version Signed-off-by:
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Bhawanpreet Lakha authored
The module works like a state machine +-------------+ ------> | Execution.c | ------ | +-------------+ | | V +----+ +--------+ +--------------+ | DM | -----> | Hdcp.c | <------------ | Transition.c | +----+ <----- +--------+ +--------------+ This patch adds the execution and transition files for 2.2 Signed-off-by: -
Bhawanpreet Lakha authored
[Why] We need these to read and write to aux/i2c, during authentication [How] Create read/write functions for all the steps (Eg, h_prime, paring_info etc) Signed-off-by:
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Bhawanpreet Lakha authored
[Why] All the HDCP transactions should be verified using PSP [How] This patch adds the psp calls we need to verify the steps Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We need some extra dmub_cmd_type for NV10 [How] Add command table functions in DMUB firmware. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Xiong Yan <Xiong.Yan@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Ilya Bakoulin authored
[Why] Need to be able to enable native 422 for debugging purposes. [How] Add new dc_debug_options bool and check it in the get_dsc_enc_caps function. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Nikola Cornij authored
[why] When updating DSC config, a new config has to be validated before proceeding with applying the update. Validation, however, modifies the current state. This means DSC config validation would affect pipe re-assignment, causing intermittent screen corruption issues when ODM is required for DSC. [how] - Use a copy of the current state for modified DSC config validation - Set the update type to FULL_UPDATE to correctly validate and set the actual state used for committing the streams Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] DCN will hang if we access registers before PHY init is done. So we need to spin or abort. [How] On hardware with DMCUB running and working we shouldn't time out waiting for this to finish and we shouldn't hit the spin cycle. If there's no hardware support then we should exit out of the function early assuming that PHY init was already done elsewhere. If we hit the timeout then there's likely a bug in firmware or software and we need to debug - add errors and asserts as appropriate. Signed-off-by:
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Jaehyun Chung authored
[Why] Need validation that we are programming the expected values (rq, ttu, dlg) from DML. This debug feature will output logs if we are programming incorrect values and may help differentiate DAL issues from HW issues. [How] Dump relevant registers for each pipe with active stream. Compare current reg values with the converted DML output. Log mismatches when found. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
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Anthony Koo authored
[Why] It is becoming increasingly hard to figure out which function is called on the different DCN versions [How] 1. Make function pointer table init in its own init.c file 2. Remove other scenarios in hwseq.c file that need to include headers of other DCN versions. (If needed, it should have been done via the function pointers) Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] It's an interface violation to use infinite loops within DMUB service functions and we'll lock up the kernel by doing so. [How] Revert the function back to its intended functionality. Move the infinite loops into DC/DM as necessary. Signed-off-by:
Sun peng Li <Sunpeng.Li@amd.com> Acked-by:
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Michael Strauss authored
[WHY] There can be a conflict between OS HDR multiplier and 3dlut HDR multiplier, which are both sent to DC. [HOW] Instead of having dc determine which HDR multiplier to use, make the decision in dm and send only the intended value in a surface update. Store the current OS HDR multiplier and determine whether to use it or the 3dlut's multiplier before sending the surface update to dc. Send multiplier to dc in fixed31_32 format, dc then converts it to hw format. Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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David (Dingchen) Zhang authored
[why] need to send immediate SDP message via debugfs on Navi board. [how] hook up the DCN1x encoder function of sending immediate sdp message to DCN2. Signed-off-by:
David (Dingchen) Zhang <dingchen.zhang@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
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Yongqiang Sun authored
[Why & How] 1. Add trace code enum for easy debugging. 2. Add trace during uC boot up, including loading phy FW and dmcu FW. 3. Change cache memory type back to write back, since write through has issue when resume from S0i3 100% hang after 3.2ms. 4. Change CW3 base address to hard code value to avoid memory overlap with cw1. 5. Change polling phy init done to infinite loop to avoid dcn hang when dmcub uC stalled. 6. Add dmcub FW dis-assembly file to repositatory for debug purpose. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Joshua Aberback authored
[Why] There is a case where the margin is between 50 and 60, but applying the workaround causes a hang. By increasing the threshold, we are blocking more cases from switching p-state during active, but those cases will fall back to switching during blank, which is fine. [How] - increase required margin from 50 to 60 Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] In the TEST_MSIC dpcd register field definition, the test equipment has the option to choose between YCbCr601 or YCbCr709. We will apply corresponding YCbCr coefficient based on this test request. [how] Add a new input parameter in dc_link_dp_set_test_pattern to allow the selection between different color space. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] Too many construct functions which makes searching difficult, especially on some debuggers. [How] Append all construct and destruct functions with dcn number and object type to make each construct function name unique Signed-off-by:
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Mikita Lipski authored
[why] Previous patch allowed to initialize debugfs entries on both MST and SST connectors, but MST connectors get registered much later which exposed an issue of debugfs entries being initialized in the same folder. [how] Return SST debugfs entries' initialization back to where it was. For MST connectors we should initialize debugfs entries in connector register function after the connector is registered. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Samson Tam authored
[Why] Hanging on RV for DTN driver verifier [How] Roll back change and investigate further Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Anthony Koo authored
[Why] Unused register in the code [How] Remove unused register Signed-off-by:
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Nikola Cornij authored
[why] In SST mode no idle pattern will be generated after link training if DIG FE is not connected to DIG BE. Signed-off-by:
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Mikita Lipski authored
[why] We were missing debugfs files on MST connectors as the files weren't initialized. [how] Move connector debugfs initialization into connoctor's init helper function so it will be called by both SST and MST connectors. Also move connector registration so it will be registered before we create the entries. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] By default we shouldn't be trying to write secure registers during DMUB hardware init. [How] Add a parameter to control whether we put the DMCUB into secure reset and attempt to load CW0/CW1. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We want to avoid reprogramming the cache window when possible. We don't need to worry about it for S3 but we *do* need to worry about it for S4 resume. DM can check whether hardware should be reinitialized or store software state when going to S4 to know whether we need to reprogram hardware. [How] Add helpers to the DMUB service to check hardware initialization state. DM will hook it up later. Signed-off-by:
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Alvin Lee authored
Changes in dc to allow for different cases where full update is required. Signed-off-by:
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Samson Tam authored
[Why] When sending DCC with Stereo, DCC gets enabled but the meta addresses are 0. This happens momentarily before the meta addresses are populated with a valid address. [How] Add call validate_dcc_with_meta_address() in copy_surface_update_to_plane() to check for surface address and DCC change. When DCC has changed, check if DCC enable is true but meta address is 0. If so, we turn DCC enable to false. When surface address has changed, we check if DCC enable is false but meta address is not 0. If so, we turn DCC enable back to true. This will restore DCC enable to the proper setting once the meta address is valid. Signed-off-by:
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Aric Cyr authored
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Stylon Wang authored
[Why] HDMI 2.0 HF-VSDB in EDID defines supported color depths in YCBCR420 modes. But we did not honor these bit masks when choosing pixel encoding. HDMI 2.0 compliance tests with deep color and YCBCR420 failed as a result. [How] Cap color depth based on y420_dc_modes from EDID. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
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Hugo Hu authored
[Why] Background color only takes effect in bottommost mpcc. [How] Update background color in bottommost mpcc. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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Leo (Hanghong) Ma authored
[Why] For debug purpose, we need to check HUBP_CLOCK_ENABLE in DTN log debugfs on Navi. [How] Add related register read in dcn20_hubp.c. Signed-off-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by:
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Joseph Gravenor authored
[why] Before we were reading registers specific to luma size, which caused a black line to appear on the screen from time to time, as although the luma row height is generally the same as the chroma row height for the video case, it will sometimes be one more [how] Read the register specific for the chroma size Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
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Joseph Gravenor authored
[why] we want to increase the pte row plus 1 line if chroma viewport height is integer multiple of the pte row height [how] instead of ceiling viewport height, we floor it. this allows us to accommodate both cases: those where the chroma viewport height is integer multiple of the pte row height and those where it is not Signed-off-by:
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abdoulaye berthe authored
Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by:
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Chris Wilson authored
An old display with no audio may not have an EDID with a CEA block, or it may simply be too old to support audio. This is not a driver error, so don't flag it as such. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112140 References: ae2a3495 ("drm/amd: be quiet when no SAD block is found") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Jean Delvare <jdelvare@suse.de> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
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zhengbin authored
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/display/modules/color/color_gamma.c: In function build_freesync_hdr: drivers/gpu/drm/amd/display/modules/color/color_gamma.c:830:20: warning: variable min_content set but not used [-Wunused-but-set-variable] It is not used since commit 50575eb5 ("drm/amd/display: Only use EETF when maxCL > max display") Reviewed-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
zhengbin <zhengbin13@huawei.com> Signed-off-by:
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zhengbin authored
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/display/dc/bios/bios_parser.c: In function bios_get_board_layout_info: drivers/gpu/drm/amd/display/dc/bios/bios_parser.c:2743:22: warning: variable bp set but not used [-Wunused-but-set-variable] It is introduced by commit 1eeedbcc ("drm/amd/display: get board layout for edid emulation"), but never used, so remove it. Reviewed-by:
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