This new function is similar to clk_set_parent(), except that it doesn't
actually change the parent. It merely checks that the given parent clock
can be a parent for the given clock.

A situation where this is useful is to check that a particular setup is
valid before switching to it. One specific use-case for this is atomic
modesetting in the DRM framework where setting a mode is divided into a
check phase where a given configuration is validated before applying
changes to the hardware.

Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

Provide CLK support for Alphascale ASM9260 SoC.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

Debugging eMMC on upstream kernels it has been noticed that when the
targetpack configures MMC0 clock to 200Mhz (required to switch to
HS200) then everything works OK. However if the kernel sets the
clock rate using clk_set_rate, then the eMMC card initialisation
fails with timeouts. Lower clock speeds (the default being 50Mhz)
work ok, but they we fail to get good eMMC transfer rates.

Looking through the vendor kernel clock driver reveals Giuseppe
had already fixed this issue, but the patch hasn't made its way
upstream.

The issue is fixed by changing the logic to manage the pdiv and
fdiv divisors used for setting the rate inside the flexgen driver code.

Pdiv is mainly targeted for low freq results, while fdiv should be
used for divs =< 64. The other way can lead to 'duty cycle'
issues.

I have changed the original patch to keep the original behaviour
in cases where the div is >64 which matches the original comment
and patch description more closely. Although no clocks appear to hit
this case currently when booting an upstream kernel.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

redefine variable clocks_per_pll as a struct member

If there are multiple PLL clock nodes, this variable will
get overwritten. Redefining it as a struct member can avoid that.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

- Clock definitions for Exynos7 SoC peripheral devices:
  video scaler, USB, DMA, SPI and the audio subsystem.

The clocks on ti81xx are not compatible with omap3. On dm816x
the clock source is a FAPLL (Flying Adder PLL), and on dm814x
there seems to be an APLL (All Digital PLL).

Let's fix up things for dm816x in preparation for adding the
FAPLL support. As we already have a dummy ti81xx_dt_clk_init()
in place, let's use that for now to avoid adding a dependency
to the omap patches.

Later on if somebody adds dm814x support we can split the
ti81xx_dt_clk_init() clock init function as needed.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.

There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.

I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:

1. Setting the PLL to bypass mode also sets the child synthesizers
   into bypass mode. As the bypass rate can also be generated by
   the PLL in regular mode, there's no way for the child synthesizers
   to detect the bypass mode based on the parent clock rate.

2. The PLL registers control the power for each of the child
   syntheriser.

Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.

I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.

This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

We don't need to fetch the parent index for clocks if they only
have one parent. Doing this also avoid an unnecessary allocation
for the parent cache.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

In case CLK_GATE_HIWORD_MASK flag is passed to clk_register_gate(), the bit #
should be no higher than 15, however the corresponding check is obviously off-
by-one.

Fixes: 04577994 ("clk: gate: add CLK_GATE_HIWORD_MASK")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

In order to fix the following section mismatch warning:
  WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference from the variable ppc_corenet_clk_driver to the function .init.text:ppc_corenet_clk_probe()
  The variable ppc_corenet_clk_driver references
  the function __init ppc_corenet_clk_probe()
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

  WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference from the variable ppc_corenet_clk_driver to the variable .init.rodata:ppc_clk_ids
  The variable ppc_corenet_clk_driver references
  the variable __initconst ppc_clk_ids
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

We can't just add the __init annotation to ppc_corenet_clk_driver or
remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids.
So choose to use CLK_OF_DECLARE to scan and init the clock devices.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

So the boards which has COMMON_CLK enabled don't have to
invoke this in its board specific file.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

The memory allocated by basic clock divider/gate/mux (struct clk_gate,
clk_divider and clk_mux) was leaking. During driver unbind or probe
failure the driver only unregistered the clocks.

Use clk_unregister_{gate,divider,mux} to release all resources.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

The common clk_register_{divider,gate,mux} functions allocated memory
for internal data which wasn't freed anywhere. Drivers using these
helpers could only unregister clocks but the memory would still leak.

Add corresponding unregister functions which will release all resources.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

The driver allows using CDCE706 in its default configuration recorded in
EEPROM and adjusting of synthesized clocks by consumers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

The commit 646cafc6 (clk: Change clk_ops->determine_rate to
return a clk_hw as the best parent) opens a possibility for
null pointer dereference, fix this.
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

This reverts commit da788acb.

That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the kernel would free the memories occupied by this struct
after boot while this driver is still registered in the driver core.
The kernel would panic when accessing this driver struct.

Cc: stable@vger.kernel.org # 3.17
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

Lockdep reported a possible deadlock between the cpuclk lock and for example
the i2c driver.

       CPU0                    CPU1
       ----                    ----
  lock(clk_lock);
                               local_irq_disable();
                               lock(&(&i2c->lock)->rlock);
                               lock(clk_lock);
  <Interrupt>
    lock(&(&i2c->lock)->rlock);

 *** DEADLOCK ***

The generic clock-types of the core ccf already use spin_lock_irqsave when
touching clock registers, so do the same for the cpuclk.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: removed initialization of "flags"]

Add required clk support for I2S, PCM and SPDIF.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Add clock support for 5 SPI channels.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Add support for PDMA0 and PDMA1 gate clks.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable
register is for nfc. Current code use bit19 for non-exist "smemc"
incorrectly, this prevents eMMC from working due to the sdhci's
"core" clk is still gated.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Cc: stable@vger.kernel.org # 3.16+
Signed-off-by: Michael Turquette <mturquette@linaro.org>

All slow clk users are not properly claiming it (get + prepare + enable)
before using it.
If all users properly claiming this clock release it, the clock is
disabled, but faulty users still depends on it, and the system hangs.

This fix prevents the slow clock from being disabled, and should solve the
hanging issue, but offending drivers should be patched to properly claim
this clock.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: Bo Shen <voice.shen@atmel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Michael Turquette <mturquette@linaro.org>

Merge tag 'v3.19-rockhip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes

- two currently unused clocks that need to stay enabled
- fix the lock bit locations of the rk3066 plls
- fix rk3288 core divider values to the ones actually
  specified by the soc vendor

Commit 0e5bdb3f (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.

The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.

Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.
Reported-by: Sonny Rao <sonnyrao@chromium.org>
Fixes: 0e5bdb3f ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Cc: stable@vger.kernel.org

The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.

The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.

Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Fixes: 2c14736c ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks")
Tested-by: FUKAUMI Naoki <naobsd@gmail.com>
Cc: stable@vger.kernel.org

Adding required gate clocks for USB3.0 DRD controller
present on Exynos7.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Add clock support for the MSCL block for Exynos7.
Signed-off-by: Tony K Nadackal <tony.kn@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Do not disable clock gate "hclk_emem_peri", otherwise EMAC clocks no longer work
and it breaks ethernet on RK3066 and RK3188. It fixes a regression introduced by
commit 78eaf609 ("clk: rockchip: disable unused clocks").
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Fixes: 78eaf609 ("clk: rockchip: disable unused clocks")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch adds CLK_IGNORE_UNUSED flag to hclk_usb_peri, hclk_usbotg0
and hclk_usbotg1 because these clocks must remain enabled to use the
USB controllers in host mode.

This fixes a regression introduced by commit 78eaf609
("clk: rockchip: disable unused clocks").
Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Fixes: 78eaf609 ("clk: rockchip: disable unused clocks")
Reviewed-by: Romain Perier <romain.perier@gmail.com>
Tested-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Pull ACCESS_ONCE cleanup preparation from Christian Borntraeger:
 "kernel: Provide READ_ONCE and ASSIGN_ONCE

  As discussed on LKML http://marc.info/?i=54611D86.4040306%40de.ibm.com
  ACCESS_ONCE might fail with specific compilers for non-scalar
  accesses.

  Here is a set of patches to tackle that problem.

  The first patch introduce READ_ONCE and ASSIGN_ONCE.  If the data
  structure is larger than the machine word size memcpy is used and a
  warning is emitted.  The next patches fix up several in-tree users of
  ACCESS_ONCE on non-scalar types.

  This does not yet contain a patch that forces ACCESS_ONCE to work only
  on scalar types.  This is targetted for the next merge window as Linux
  next already contains new offenders regarding ACCESS_ONCE vs.
  non-scalar types"

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linux:
  s390/kvm: REPLACE barrier fixup with READ_ONCE
  arm/spinlock: Replace ACCESS_ONCE with READ_ONCE
  arm64/spinlock: Replace ACCESS_ONCE READ_ONCE
  mips/gup: Replace ACCESS_ONCE with READ_ONCE
  x86/gup: Replace ACCESS_ONCE with READ_ONCE
  x86/spinlock: Replace ACCESS_ONCE with READ_ONCE
  mm: replace ACCESS_ONCE with READ_ONCE or barriers
  kernel: Provide READ_ONCE and ASSIGN_ONCE

Pull clk framework updates from Mike Turquette:
 "This is much later than usual due to several last minute bugs that had
  to be addressed.  As usual the majority of changes are new drivers and
  modifications to existing drivers.  The core recieved many fixes along
  with the groundwork for several large changes coming in the future
  which will better parition clock providers from clock consumers"

* tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
  ARM: OMAP3: clock: fix boot breakage in legacy mode
  ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs
  clk: Really fix deadlock with mmap_sem
  clk: mmp: fix sparse non static symbol warning
  clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
  clk: change clk_debugfs_add_file to take a struct clk_hw
  clk: Don't expose __clk_get_accuracy
  clk: Don't try to use a struct clk* after it could have been freed
  clk: Remove unused function __clk_get_prepare_count
  clk: samsung: Fix double add of syscore ops after driver rebind
  clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
  clk: samsung: exynos4415: Fix build with PM_SLEEP disabled
  clk: samsung: remove unnecessary inclusion of header files from clk.h
  clk: samsung: remove unnecessary CONFIG_OF from clk.c
  clk: samsung: Spelling s/bwtween/between/
  clk: rockchip: Add support for the mmc clock phases using the framework
  clk: rockchip: add bindings for the mmc clocks
  clk: rockchip: rk3288 export i2s0_clkout for use in DT
  clk: rockchip: use clock ID for DMC (memory controller) on rk3288
  ...

Pull more i2c updates from Wolfram Sang:
 "Included are two bugfixes needing some bigger refactoring (sh_mobile:
  deferred probe with DMA, mv64xxx: fix offload support) and one
  deprecated driver removal I thought would go in via ppc but I
  misunderstood.  It has a proper ack from BenH"

* 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  i2c: sh_mobile: fix uninitialized var when debug is enabled
  macintosh: therm_pm72: delete deprecated driver
  i2c: sh_mobile: I2C_SH_MOBILE should depend on HAS_DMA
  i2c: sh_mobile: rework deferred probing
  i2c: sh_mobile: refactor DMA setup
  i2c: mv64xxx: rework offload support to fix several problems
  i2c: mv64xxx: use BIT() macro for register value definitions

Pull SCSI update from James Bottomley:
 "This is a much shorter set of patches that were on the go but didn't
  make it in to the early pull request for the merge window.  It's
  really a set of bug fixes plus some final cleanup work on the new tag
  queue API"

* tag 'scsi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi:
  storvsc: ring buffer failures may result in I/O freeze
  ipr: set scsi_level correctly for disk arrays
  ipr: add support for async scanning to speed up boot
  scsi_debug: fix missing "break;" in SDEBUG_UA_CAPACITY_CHANGED case
  scsi_debug: take sdebug_host_list_lock when changing capacity
  scsi_debug: improve driver description in Kconfig
  scsi_debug: fix compare and write errors
  qla2xxx: fix race in handling rport deletion during recovery causes panic
  scsi: blacklist RSOC for Microsoft iSCSI target devices
  scsi: fix random memory corruption with scsi-mq + T10 PI
  Revert "[SCSI] mpt3sas: Remove phys on topology change"
  Revert "[SCSI] mpt2sas: Remove phys on topology change."
  esas2r: Correct typos of "validate" in a comment
  fc: FCP_PTA_SIMPLE is 0
  ibmvfc: remove unused tag variable
  scsi: remove MSG_*_TAG defines
  scsi: remove scsi_set_tag_type
  scsi: remove scsi_get_tag_type
  scsi: never drop to untagged mode during queue ramp down
  scsi: remove ->change_queue_type method

Pull CONFIG_PM_RUNTIME elimination from Rafael Wysocki:
 "This removes the last few uses of CONFIG_PM_RUNTIME introduced
  recently and makes that config option finally go away.

  CONFIG_PM will be available directly from the menu now and also it
  will be selected automatically if CONFIG_SUSPEND or CONFIG_HIBERNATION
  is set"

* tag 'pm-config-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
  PM: Eliminate CONFIG_PM_RUNTIME
  tty: 8250_omap: Replace CONFIG_PM_RUNTIME with CONFIG_PM
  sound: sst-haswell-pcm: Replace CONFIG_PM_RUNTIME with CONFIG_PM
  spi: Replace CONFIG_PM_RUNTIME with CONFIG_PM

Pull misc kbuild changes from Michal Marek:
 "There are only a few things in the misc branch:

   - Fix for bugon.cocci semantic patch
   - Kdevelop4 files are .gitignored
   - Put make binrpm-pkg on diet"

* 'misc' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild:
  scripts/package: binrpm-pkg do not create source and devel package
  .gitignore: Add Kdevelop4 project files
  bugon.cocci: fix Options at the macro

Pull kbuild updates from Michal Marek:
 "Here are the kbuild changes for v3.19-rc1:

   - Cleanups and deduplication in the main Makefile and
     scripts/Makefile.*
   - Sort the output of *config targets in make help
   - Old <linux/version.h> is always removed to avoid a surprise during
     bisecting
   - Warning fix in kconfig"

* 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild:
  kbuild: remove redundant -rR flag of hdr-inst
  kbuild: Fix make help-<board series> on powerpc
  kbuild: Automatically remove stale <linux/version.h> file
  kconfig: Fix warning "‘jump’ may be used uninitialized"
  Makefile: sort list of defconfig targets in make help output
  kbuild: Remove duplicate $(cmd) definition in Makefile.clean
  kbuild: collect shorthands into scripts/Kbuild.include

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>