- 11 Nov, 2019 18 commits
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Olof Johansson authored
Merge tag 'tegra-for-5.5-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers memory: tegra: Changes for v5.5-rc1 This contains a couple of fixes and adds support for EMC frequency scaling on Tegra30. * tag 'tegra-for-5.5-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits clk: tegra: Add Tegra20/30 EMC clock implementation Link: https://lore.kernel.org/r/20191111143836.4027200-1-thierry.reding@gmail.comSigned-off-by:
Olof Johansson <olof@lixom.net>
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git://github.com/hisilicon/linux-hisiOlof Johansson authored
ARM64: hisi: SoC driver updates for 5.5 - check the LOGIC_PIO_INDIRECT region ops at registration instead of in the IO port accessors to optimise the lib/ligic_pio.c - add the hisi LPC driver to the build test for the other architectures except ALPHA, C6X, HEXAGON and PARISC as they do not define {read,write}sb by updating the hisi LPC Kconfig and adding a dummy PIO_INDIRECT_SIZE - clean the sparse complains of the hisi LPC driver - build logic_pio into a lib to avoid including in the vmlinux when not referenced * tag 'hisi-drivers-for-5.5' of git://github.com/hisilicon/linux-hisi: logic_pio: Build into a library bus: hisi_lpc: Expand build test coverage bus: hisi_lpc: Clean some types logic_pio: Define PIO_INDIRECT_SIZE for !CONFIG_INDIRECT_PIO lib: logic_pio: Enforce LOGIC_PIO_INDIRECT region ops are set at registration Link: https://lore.kernel.org/r/5DC959B9.80301@hisilicon.comSigned-off-by: -
Olof Johansson authored
Merge tag 'v5.4-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers refactor code of mtk-scpsys * tag 'v5.4-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: soc: mediatek: Refactor bus protection control soc: mediatek: Refactor sram control soc: mediatek: Refactor clock control soc: mediatek: Refactor regulator control soc: mediatek: Refactor polling timeout and documentation Link: https://lore.kernel.org/r/294422a4-37b2-def5-5d32-8988f27c3a5b@gmail.comSigned-off-by:
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Dmitry Osipenko authored
The Memory Controller registers definition is sparse and duplicated, let's consolidate everything into a common place for consistency. Acked-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Dmitry Osipenko authored
Timing control debug features should be disabled at a boot time, but you never now and hence it's better to disable them explicitly because some of those features are crucial for the driver to do a proper thing. Acked-by:
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Dmitry Osipenko authored
Introduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Acked-by:
Peter Geis <pgwipeout@gmail.com> Signed-off-by:
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Dmitry Osipenko authored
Contrary to its wait_for_completion_timeout_interruptible() sibling, the wait_for_completion_timeout() function does not return an error. Signed-off-by:
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Dmitry Osipenko authored
Turned out that it could take over a millisecond under some circumstances, like running on a very low CPU/memory frequency. TRM says that handshake happens when there is a "safe" moment, but not explains exactly what that moment is. Apparently at least memory should be idling and thus the low frequency should be a reasonable cause for a longer handshake delay. Signed-off-by:
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Dmitry Osipenko authored
During boot print how many memory timings got the driver and what's the RAM code. This is a very useful information when something is wrong with boards memory timing. Suggested-by:
Marc Dietrich <marvin24@gmx.de> Signed-off-by:
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Dmitry Osipenko authored
The driver expects certain debug features to be disabled in order to work properly. Let's disable them explicitly for consistency and to not rely on a boot state. Acked-by:
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Dmitry Osipenko authored
The register polling code was gone, but the included header change was missed. Fix it up for consistency. Acked-by:
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Dmitry Osipenko authored
Now Tegra20 and Tegra30 EMC drivers should provide clock-rounding functionality using the new Tegra clock driver API. Acked-by:
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Dmitry Osipenko authored
The memory frequency scaling will be managed by tegra20-devfreq driver and PM QoS once all the prerequisite patches will get upstreamed. The parent clock is now managed by the clock driver and we also should assume that PLLM rate can't be changed on some devices (Galaxy Tab 10.1 for example). Altogether there is no point in touching of clock's rate from the EMC driver. Acked-by:
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Thierry Reding authored
All of the devices making up the Tegra DRM device want to share a single IOMMU domain. Put them into a single group to allow them to do that. Signed-off-by: -
Thierry Reding authored
The memory controller on Tegra124 and later supports 34 or more address bits. Advertise that by setting the DMA mask based on the number of the address bits. Signed-off-by: -
Thierry Reding authored
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Dmitry Osipenko authored
A proper External Memory Controller clock rounding and parent selection functionality is required by the EMC drivers, it is not available using the generic clock implementation because only the Memory Controller driver is aware of what clock rates are actually available for a particular device. EMC drivers will have to register a Tegra-specific CLK-API callback which will perform rounding of a requested rate. EMC clock users won't be able to request EMC clock by getting -EPROBE_DEFER until EMC driver is probed and the callback is set up. The functionality is somewhat similar to the clk-emc.c which serves Tegra124+ SoCs. The later HW generations support more parent clock sources and the HW configuration / integration with the EMC drivers differs a tad from the older gens, hence it's not really worth to try to squash everything into a single source file. Acked-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Olof Johansson authored
Merge tag 'amlogic-drivers' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/drivers soc: amlogic: updates for v5.5 Highlights - socinfo: more SoC IDs - firmware: misc secure-monitor cleanups * tag 'amlogic-drivers' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: soc: amlogic: meson-gx-socinfo: Fix S905D3 ID for VIM3L soc: amlogic: meson-gx-socinfo: Add S905X3 ID for VIM3L soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs firmware: meson_sm: use %*ph to print small buffer firmware: meson_sm: Rework driver as a proper platform driver nvmem: meson-efuse: bindings: Add secure-monitor phandle firmware: meson_sm: Mark chip struct as static const Link: https://lore.kernel.org/r/7hftivs11f.fsf@baylibre.comSigned-off-by:
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- 08 Nov, 2019 2 commits
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Olof Johansson authored
Merge tag 'at91-5.5-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/drivers AT91 drivers for 5.5 - a new driver exposing the serial number registers through nvmem - a few documentation and definition changes * tag 'at91-5.5-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver ARM: at91: Documentation: update the sama5d3 and armv7m datasheets Link: https://lore.kernel.org/r/20191107221644.GA201884@piout.netSigned-off-by:
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https://github.com/Xilinx/linux-xlnxOlof Johansson authored
arm64: soc: Xilinx SoC changes for v5.5 - Extend firmware interface to cover Versal chip * tag 'zynqmp-soc-for-v5.5' of https://github.com/Xilinx/linux-xlnx: firmware: xilinx: Add support for versal soc dt-bindings: firmware: Add bindings for Versal firmware soc: xilinx: Set CAP_UNUSABLE requirement for versal while powering down domain Link: https://lore.kernel.org/r/6954a53c-6dab-c7a3-7257-58460ca952cb@monstr.euSigned-off-by:
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- 07 Nov, 2019 8 commits
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Kamel Bouhara authored
Add support to read SFR's read-only registers providing the SoC Serial Numbers (SN0+SN1) to userspace. ~ # hexdump -n 8 -e'"%d\n"' /sys/bus/nvmem/devices/atmel-sfr0/nvmem 959527243 371539274 Signed-off-by:
Kamel Bouhara <kamel.bouhara@bootlin.com> Tested-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by:
Alexandre Belloni <alexandre.belloni@bootlin.com>
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Tudor Ambarus authored
Adopt the SPDX license identifiers to ease license compliance management. Signed-off-by:
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Tudor Ambarus authored
The total number of EBI CS lines is described by the EBI controller and not by the Matrix. Move the definition for the number of CS inside EBI driver. Signed-off-by:
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Weiyi Lu authored
Put bus protection enable and disable control in separate functions. Signed-off-by:
Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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Weiyi Lu authored
Put sram enable and disable control in separate functions. Signed-off-by:
Nicolas Boichat <drinkcat@chromium.org> [mb: fix coding style of reading register and changing the read value] Signed-off-by:
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Weiyi Lu authored
Put clock enable and disable control in separate function. Signed-off-by:
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Weiyi Lu authored
Put regulator enable and disable control in separate functions. Signed-off-by:
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Weiyi Lu authored
Use USEC_PER_SEC to indicate the polling timeout directly. And add documentation of scp_domain_data. Signed-off-by:
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- 06 Nov, 2019 4 commits
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Olof Johansson authored
Merge tag 'qcom-drivers-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm ARM Based Driver Updates for v5.5 * Add Bjorn as QCOM co-maintainer * Add LLLC yaml bindings and SC7180 support * Fixups/Cleanup for LLLC * Add SMD-RPM MSM8976 compatible and interconnect device * Add missing RPMD SMD perf level * tag 'qcom-drivers-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: MAINTAINERS: Add myself as co-maintainer for QCOM dt-bindings: msm: Add LLCC for SC7180 dt-bindings: msm: Convert LLCC bindings to YAML soc: qcom: llcc: Add configuration data for SC7180 soc: qcom: llcc: Move regmap config to local variable soc: qcom: llcc: Name regmaps to avoid collisions soc: qcom: Fix llcc-qcom definitions to include soc: qcom: rpmpd: Add rpm power domains for msm8976 dt-bindings: power: Add missing rpmpd smd performance level soc: qcom: smd-rpm: Add MSM8976 compatible soc: qcom: socinfo: add sdm845 and sda845 soc ids soc: qcom: smd-rpm: Create RPM interconnect proxy child device soc: qcom: Make llcc-qcom a generic driver soc: qcom: Rename llcc-slice to llcc-qcom soc: qcom: llcc cleanup to get rid of sdm845 specific driver file Link: https://lore.kernel.org/r/1573068840-13098-4-git-send-email-agross@kernel.orgSigned-off-by:
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Christian Hewitt authored
Chip on the board is S905D3 not S905X3: [ 0.098998] soc soc0: Amlogic Meson SM1 (S905D3) Revision 2b:c (b0:2) Detected Change from v1: use 0xf0 mask instead of 0xf2 as advised by Neil Armstrong. Fixes: 1d7c541b ("soc: amlogic: meson-gx-socinfo: Add S905X3 ID for VIM3L") Signed-off-by:
Christian Hewitt <christianshewitt@gmail.com> Acked-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Kevin Hilman <khilman@baylibre.com>
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Olof Johansson authored
Merge tag 'imx-drivers-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers update for 5.5: - Skip return check for those SCU firmware APIs that are defined as void function in firmware. - Use established serial_number attribute instead of custom one to show SoC's unique ID for i.MX8 SoC drivers. - Read i.MX8MQ SOC revision from TF-A which parses ROM and exposes the value through a SMC call. This improves the situation that SOC revision reports 'unknown' on some older revisions. - Add a check and warn on unexpected SCU RX to avoid potential stack corruption in imx-scu driver. - Fix a sparse warning in imx-scu-irq driver by adding missing header. - Remove an unneeded call to devm_of_platform_populate() from imx-dsp driver. * tag 'imx-drivers-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx8mq: Read SOC revision from TF-A soc: imx-scu: Using existing serial_number instead of UID soc: imx8: Using existing serial_number instead of UID firmware: imx: add missing include of <linux/firmware/imx/sci.h> firmware: imx: Remove call to devm_of_platform_populate firmware: imx: Skip return value check for some special SCU firmware APIs firmware: imx: warn on unexpected RX Link: https://lore.kernel.org/r/20191105150315.15477-1-shawnguo@kernel.orgSigned-off-by:
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Olof Johansson authored
Merge tag 'samsung-drivers-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers Samsung soc drivers changes for v5.5 1. Minor fixes to Exynos Chipid driver. 2. Add Exynos Adaptive Supply Voltage driver allowing to adjust voltages used during CPU frequency scaling based on revision of SoC. This also pulls dependency from PM/OPP tree - driver uses newly added dev_pm_opp_adjust_voltage() function. * tag 'samsung-drivers-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: soc: samsung: exynos-asv: Potential NULL dereference in exynos_asv_update_opps() soc: samsung: chipid: Drop "syscon" compatible requirement soc: samsung: Add Exynos Adaptive Supply Voltage driver PM / OPP: Support adjusting OPP voltages at runtime soc: samsung: chipid: Make exynos_chipid_early_init() static Link: https://lore.kernel.org/r/20191104175902.12224-1-krzk@kernel.orgSigned-off-by:
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- 05 Nov, 2019 6 commits
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Bjorn Andersson authored
Add myself as co-maintainer for the Qualcomm SoC. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Andy Gross <agross@kernel.org>
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John Garry authored
Object file logic_pio.o is always built. Ideally the object file should only be built when required. This is tricky, as that would be for archs which define PCI_IOBASE, but no common config option exists for that. For now, continue to always build but at least ensure the symbols are not included in the vmlinux when not referenced. Suggested-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
John Garry <john.garry@huawei.com> Signed-off-by:
Wei Xu <xuwei5@hisilicon.com>
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John Garry authored
Currently the driver will only ever be built for ARM64 because it selects CONFIG_INDIRECT_PIO, which itself depends on ARM64. Expand build test coverage for the driver to other architectures by only selecting CONFIG_INDIRECT_PIO for ARM64, when we really want it. We don't include ALPHA, C6X, HEXAGON, and PARISC architectures as they don't define {read, write}sb. Signed-off-by: -
John Garry authored
Sparse complains of these: drivers/bus/hisi_lpc.c:82:38: warning: incorrect type in argument 1 (different address spaces) drivers/bus/hisi_lpc.c:82:38: expected void const volatile [noderef] <asn:2>*addr drivers/bus/hisi_lpc.c:82:38: got unsigned char * drivers/bus/hisi_lpc.c:131:35: warning: incorrect type in argument 1 (different address spaces) drivers/bus/hisi_lpc.c:131:35: expected unsigned char *mbase drivers/bus/hisi_lpc.c:131:35: got void [noderef] <asn:2>*membase drivers/bus/hisi_lpc.c:186:35: warning: incorrect type in argument 1 (different address spaces) drivers/bus/hisi_lpc.c:186:35: expected unsigned char *mbase drivers/bus/hisi_lpc.c:186:35: got void [noderef] <asn:2>*membase drivers/bus/hisi_lpc.c:228:16: warning: cast to restricted __le32 drivers/bus/hisi_lpc.c:251:13: warning: incorrect type in assignment (different base types) drivers/bus/hisi_lpc.c:251:13: expected unsigned int [unsigned] [usertype] val drivers/bus/hisi_lpc.c:251:13: got restricted __le32 [usertype] <noident> Clean them up. Signed-off-by:
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John Garry authored
With the goal of expanding the test coverage of the HiSi LPC driver to !ARM64, define a dummy PIO_INDIRECT_SIZE for !CONFIG_INDIRECT_PIO, which is required by the named driver. Signed-off-by:
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John Garry authored
Since the only LOGIC_PIO_INDIRECT host (hisi-lpc) now sets the ops prior to registration, enforce this check for accessors ops at registration instead of in the IO port accessors to simplify and marginally optimise the code. A slight misalignment is also tidied. Also add myself as an author. Suggested-by:
Bjorn Helgaas <bhelgaas@google.com> Signed-off-by:
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- 04 Nov, 2019 2 commits
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Leonard Crestez authored
SOC revision on older imx8mq is not available in fuses so on anything other than B1 current code just reports "unknown". TF-A already handles this by parsing the ROM and exposes the value through a SMC call. Call this instead of reimplementing the workaround in the kernel itself. Signed-off-by:
Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by:
Abel Vesa <abel.vesa@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Olof Johansson authored
Merge tag 'tegra-for-5.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc/tegra: Changes for v5.5-rc1 Adds wake event support on Tegra210, implements the NVMEM API for the Tegra FUSE block and adds coupled regulators support for Tegra20 and Tegra30. * tag 'tegra-for-5.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Remove unnecessary memory barrier soc/tegra: pmc: Query PCLK clock rate at probe time soc/tegra: regulators: Add regulators coupler for Tegra30 soc/tegra: regulators: Add regulators coupler for Tegra20 soc/tegra: pmc: Configure deep sleep control settings soc/tegra: pmc: Configure core power request polarity soc/tegra: pmc: Add wake event support on Tegra210 soc/tegra: pmc: Support wake events on more Tegra SoCs soc/tegra: fuse: Register cell lookups for compatibility soc/tegra: fuse: Add cell information soc/tegra: fuse: Implement nvmem device soc/tegra: fuse: Restore base on sysfs failure soc/tegra: pmc: Fix crashes for hierarchical interrupts soc/tegra: fuse: Add FUSE clock check in tegra_fuse_readl() Link: https://lore.kernel.org/r/20191102144521.3863321-4-thierry.reding@gmail.comSigned-off-by:
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