- 25 Jan, 2021 7 commits
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Colin Ian King authored
Currently the ! operator is incorrectly being used to flip bits on mask values. Fix this by using the bit-wise ~ operator instead. Addresses-Coverity: ("Logical vs. bitwise operator") Fixes: 3c9a7b7d ("drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3") Reviewed-by:Huang Rui <ray.huang@amd.com> Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Arunpravin authored
store swsmu user power configurations which include power limit, clock frequencies, fan speed and fan mode on suspend and reinstate on resume. V2: Addressed Lijo's review comments added a function to set clock interdependencies add check on fan control mode to reapply fan speed V3: Addressed review comments from Alex moved store logic and reinstate function call into swSMU V4: added a logic to keep off storing configurations in suspend V5: Addressed review comments from Lijo add a restore flag give restore priority to mclk comparing fclk and socclk Signed-off-by:Arunpravin <Arunpravin.PaneerSelvam@amd.com> Acked-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Jingwen Chen authored
[Why] when vram lost happened in guest, try to write vram can lead to kernel stuck. [How] When the readback data is invalid, don't do write work, directly reschedule a new work. Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Monk Liu<monk.liu@amd.com> Signed-off-by:
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Lang Yu authored
Replace "/" with div_u64 for 32-bit OS. On 32-bit OS, the use of "/" for 64-bit division will cause build error, i.e. "__udivdi3/__divdi3 undefined!". Fixes: ea7154d8 ("drm/amd/display: Update dcn30_apply_idle_power_optimizations() code") Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Pratik Vishwakarma authored
This reverts commit 57eeaf47. Original issue of flash line when MPO enabled on idle screen was fixed by raising clocks. This had negative effect of extra power being drained. With the upstream commit 9d03bb10 ("drm/amd/display: disable dcn10 pipe split by default") flash line issue was fixed and had positive effect for battery life. Hence this patch is no more required. Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Horace Chen authored
Fix a racing issue when jobs on 2 rings timeout simultaneously. If 2 rings timed out at the same time, the amdgpu_device_gpu_recover will be reentered. Then the adev->gmc.xgmi.head will be grabbed by 2 local linked list, which may cause wild pointer issue in iterating. lock the device earily to prevent the node be added to 2 different lists. also increase karma for the skipped job since the job is also timed out and should be guilty. Signed-off-by:
Horace Chen <horace.chen@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Felix Kuehling authored
Enable pinning of VRAM without forcing it to be contiguous. When memory is already pinned, make sure it's contiguous if requested. Suggested-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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- 21 Jan, 2021 13 commits
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Huang Rui authored
The ip discovery is supported on green sardine, it doesn't need gpu info firmware anymore. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Signed-off-by:
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Felix Kuehling authored
ROCm user mode depends on userptr support. Without it, KFD is basically useless. Make sure HSA_AMD selects the same options as DRM_AMDGPU_USERPTR to avoid broken configurations where userptr gets enabled but its dependencies are disabled. Signed-off-by:
Philip Yang <philip.yang@amd.com> Signed-off-by:
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Huang Rui authored
This patch is to help firmware designer to know the smc message timeout status. Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Feifei Xu authored
Add PCIE_SPEED_32_0GT and PCIE GEN5 support for amdgpu. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Acked-by:
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Jinzhou Su authored
Send allow GfxOff message to SMU to enter GfxOff mode as default. Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by:
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Jiapeng Zhong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c: 1009:6-16: WARNING: Assignment of 0/1 to bool variable. ./drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c: 200:2-10: WARNING: Assignment of 0/1 to bool variable. Reviewed-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Zhong <abaci-bugfix@linux.alibaba.com> Signed-off-by:
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Colin Ian King authored
There are two spelling mistakes of the function name, fix this by using __func__ instead of a hard coded name string. Reviewed-by:
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Bhawanpreet Lakha authored
Update the function for idle optimizations -remove hardcoded size -enable no memory-request case -add cursor copy -update mall eligibility check case Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] Currently we use the maximum possible cursor cache size when deciding if we should attempt to enable MALL, but this prevents us from enabling the feature for certain key use cases. [How] - consider cursor bpp when calculating if the cursor fits Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
-Uncomment watermark set d -This populates the wm table so that it can be sent to PMFW -This watermark table is used when we are in mall stutter Signed-off-by:
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Aaron Liu authored
Starting from vangogh, the ATCL2 and DAGB0 registers relative to mgcg/ls has changed. For MGCG: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. For MGLS: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Acked-by:
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Jinzhou Su authored
Driver should enable the CGPG feature for RLC in safe mode to prevent any misalignment or conflict in middle of any power feature entry/exit sequence. Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1, and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value in refclk count. Reviewed-by:
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Prike Liang authored
In the renoir there is no need GpuChangeState message set to exit gfxoff in the s0i3 resume since mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL has been added in the s0i3 FSDL. Signed-off-by:
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- 20 Jan, 2021 20 commits
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Jinzhou Su authored
GCR_GENERAL_CNTL is defined differently in gc_10_1_0_offset.h and gc_10_3_0_offset.h. Update GCR_GENERAL_CNTL for Vangogh. Signed-off-by:
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Jinzhou Su authored
1. Remove PP_GFXOFF_MASK and then GFXOFF can be enabled by user space. 2. GFXOFF is still disabled on Vangogh by default. 3. When GFXOFF feature on Vangogh landed, will enable GFXOFF by default. 4. GFXOFF can be enabled by debugfs interface amdgpu_gfxoff. Signed-off-by: -
Aric Cyr authored
Signed-off-by:
Anson Jacob <anson.jacob@amd.com> Signed-off-by:
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Anthony Koo authored
Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Jake Wang authored
[WHY] dram clock change latencies get updated using ddr4 latency table, but that update does not happen before validation. This value should not be the default and should be number received from df for better mode support. This may cause a PState hang on high refresh panels with short vblanks such as on 1080p 360hz or 300hz panels. [HOW] Update latency from 23.84 to 11.72. Tested-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
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Aric Cyr authored
[Why] When no displays are currently enabled, display driver should not disallow PSTATE switching. [How] Allow PSTATE switching if either the active configuration supports it, or there are no active displays. Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Bing Guo authored
Why: dml20v2_ModeSupportAndSystemConfigurationFull() didn't check against DesiredBPP, so it doesn't work correctly when DesiredBPP can't be satisfied. How: Port the TruncToValidBPP() version from display_mode_vba_21.c to display_mode_vba_20v2.c. Tested-by:
Bing Guo <bing.guo@amd.com> Reviewed-by:
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George Shen authored
[Why/How] Add logging statements to assist in debugging errors in the BIOS object table. Tested-by:
George Shen <george.shen@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] FW version check doesn't allow dmu_stg to support cached inbox, which yields much better performance than region 4. [How] Check a range of fw versions, rather than a simple greater than check. Tested-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Bing Guo authored
Why: Function decide_dp_link_settings() loops infinitely when required bandwidth can't be supported. How: Check the required bandwidth against verified_link_cap before trying to find a link setting for it. Tested-by:
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Nicholas Kazlauskas authored
[Why] DMCUB encounters a page fault/double exception with driver direct load because DMCUB is not held in soft reset after releasing secure reset. The clean shutdown sequence via GPINT is also not executed in this sequence which leaves hardware behavior in an indeterminate state. [How] Move reset earlier in the sequence. Tested-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] If the BIOS table is invalid or corrupt then get_i2c_info can fail and we dereference a NULL pointer. [How] Check that ddc_pin is not NULL before using it and log an error if it is because this is unexpected. Tested-by:
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Nicholas Kazlauskas authored
[Why] We need hardware reset before hardware init for backdoor loading when we're reusing the framebuffer memory. [How] This doesn't run if the hardware isn't already in reset from software perspective. The reset function has register level checks so just remove the software one here. Tested-by:
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Stylon Wang authored
[Why] Since Linux 5.9.0, DRM has provided vrr_range debugfs for all connectors. Reporting Freesync capability to vrr_range debugfs entry registered in Linux DM no longer works. [How] Report min/max vertical frequency to vrr_range debugfs entrry created by DRM connectors. Remove vrr_range debugfs entry from Linux DM. Tested-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why & How] These can differ per ASIC or not be present. Don't call the dcn20 ones directly but rather the ones defined by the ASIC init table. Tested-by:
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Sung Lee authored
[WHY] Previously as MPO + ODM Combine was not supported, finding secondary pipes for each case was mutually exclusive. Now that both are supported at the same time, both cases should be taken into account when finding a secondary pipe. [HOW] If a secondary pipe cannot be found based on previous bottom pipe, search for a second pipe using next_odm_pipe instead. Tested-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Mike Hsieh authored
[Why] FEC over eDP support is incomplete. [How] Disable FEC over eDP. Tested-by:
Mike Hsieh <chun-wei.hsieh@amd.com> Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Vladimir Stempen authored
[why] Heavy corruption or blank screen reported on wake, with 6k display connected and FEC enabled [how] When Disable/Enable stream for display pipes on HPDRX, DC should take into account ODM split pipes. Tested-by:
Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by:
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Jingwen Chen authored
When using cancel_delayed_work_sync, there's no need to flush_delayed_work first. This sequence can lead to a redundant loop of work executing. Signed-off-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Kevin Wang authored
the SpareX is reserved by SMU firmware, the driver is never use it. Signed-off-by:
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