- 05 Dec, 2023 7 commits
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Amritha Nambiar authored
Add support in netlink spec(netdev.yaml) for interrupt number among the NAPI attributes. Add code generated from the spec. Signed-off-by:
Amritha Nambiar <amritha.nambiar@intel.com> Reviewed-by:
Sridhar Samudrala <sridhar.samudrala@intel.com> Link: https://lore.kernel.org/r/170147334210.5260.18178387869057516983.stgit@anambiarhost.jf.intel.comSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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Amritha Nambiar authored
Implement the netdev netlink framework functions for napi support. The netdev structure tracks all the napi instances and napi fields. The napi instances and associated parameters can be retrieved this way. Signed-off-by:
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Amritha Nambiar authored
Add support in netlink spec(netdev.yaml) for napi related information. Add code generated from the spec. Signed-off-by:
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Amritha Nambiar authored
Implement the netdev netlink framework functions for exposing queue information. Signed-off-by:
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Amritha Nambiar authored
After the napi context is initialized, map the napi instance with the queue/queue-set on the corresponding irq line. Signed-off-by:
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Amritha Nambiar authored
Add the napi pointer in netdev queue for tracking the napi instance for each queue. This achieves the queue<->napi mapping. Signed-off-by:
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Amritha Nambiar authored
Add support in netlink spec(netdev.yaml) for queue information. Add code generated from the spec. Note: The "queue-type" attribute takes values 0 and 1 for rx and tx queue type respectively. Signed-off-by:
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- 04 Dec, 2023 24 commits
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Jakub Kicinski authored
Michael Chan says: ==================== bnxt_en: Support new 5760X P7 devices This series completes the basic support for the new 5760X P7 devices with new PCI IDs added in the last patch. Thie first patch fixes a backing store issue introduced in the last patchset last week. The 2nd patch is the new firmware interface required to support the new chips. The next few patches are doorbell changes, refactoring, and new hardware interface structures. New changes to support packet reception including TPA are added in patch 10. The next 4 patches are ethernet link related changes to support the new chip. ==================== Link: https://lore.kernel.org/r/20231201223924.26955-1-michael.chan@broadcom.comSigned-off-by:
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Michael Chan authored
Now with basic support for the new chip family, add the PCI IDs of the new devices. Reviewed-by:
Andy Gospodarek <gospo@broadcom.com> Signed-off-by:
Michael Chan <michael.chan@broadcom.com> Link: https://lore.kernel.org/r/20231201223924.26955-16-michael.chan@broadcom.comSigned-off-by:
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Michael Chan authored
Add new look up entries to convert the new supported speeds, advertised speeds, etc to ethtool link modes. Reviewed-by:
Damodharam Ammepalli <damodharam.ammepalli@broadcom.com> Signed-off-by:
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Michael Chan authored
Modify bnxt_force_link_speed() to support the new speeds stored in link_info->support_speeds2, including the new 400G speed. Reviewed-by:
Ajit Khaparde <ajit.khaparde@broadcom.com> Signed-off-by:
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Michael Chan authored
Newer firmware supporting PAM4 112Gbps speeds use new parameters in firmware message structures. Detect the new firmware capability and add basic logic to report and store these new fields. Reviewed-by:
Hongguang Gao <hongguang.gao@broadcom.com> Reviewed-by:
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Michael Chan authored
Add helper functions to refactor the logic that converts firmware speed masks to ethtool speeds. Pass the phy_flags to bnxt_get_ethtool_speeds() and the call chain. The refactoring and the phy_flags will be needed when adding support for the new speeds in the next patches. Reviewed-by:
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Michael Chan authored
These new completion types are supported on the new P7 chips. These new types have commonalities with the legacy types. After the refactoring, we mainly have to add new functions to handle the the new meta data formats and the RX hash information in the new types. Signed-off-by:
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Michael Chan authored
Refactor bnxt_tpa_start() by adding bnxt_tpa_metadata() to gather the metadata from the TPA_START completion. This makes it easier to support the new P7 chip which has a modified TPA_START completion structure with different metadata formats. We also add vlan_valid and cfa_code_valid fields to the bnxt_tpa_info structure so that the VLAN and VF rep logic can be common for all chips. The VLAN metadata is now collected in bnxt_tpa_start() only when it is valid and the vlan_valid field will be set. bnxt_tpa_end() can now use common VLAN logic for all chips. Signed-off-by:
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Michael Chan authored
Refactor the logic in the RX path that checks for the accelerated VLAN tag by adding a new function. This will make it easier to support the new receive logic on P7 chips. Reviewed-by:
Pavan Chebbi <pavan.chebbi@broadcom.com> Signed-off-by:
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Michael Chan authored
Add new RX, TX, and TPA hardware interface structures and macros for the P7 chips. Reviewed-by:
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Ajit Khaparde authored
Add a new rss_cap field in the per device struct bnxt and move all the RSS capability fields there. It will be easier to add new RSS capabilities for the new P7 chips. Signed-off-by:
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Michael Chan authored
The new chip family passes the Toggle bits to the driver in the NQE notification. The driver now stores this value and sends it back to hardware when it re-arms the RX and TX CQs. Together with the earlier patch that guarantees the driver will only re-arm the CQ at the end of NAPI polling if it has seen a new NQE, this method allows the hardware to detect any dropped doorbells. Signed-off-by:
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Hongguang Gao authored
The doorbell offset on P5 chips is hard coded. On the new P7 chips, it is returned by the firmware. Simplify the logic that determines this offset and store it in a new db_offset field in struct bnxt. Also, provide this offset to the RoCE driver in struct bnxt_en_dev. Reviewed-by:
Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Signed-off-by:
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Michael Chan authored
Repurpose the BNXT_FLAG_CHIP_SR2 flag by renaming it to BNXT_FLAG_CHIP_P7 since the SR2 chip never went to production. The SR2 statictics structure is also renamed for the P7 chip. Define the basic P7 doorbell bits (Epoch. Toggle, etc) and implement the Epoch bit logic. The next higher bit beyond the legal doorbell mask is the Epoch bit used for doorbells on P7 chips. This bit is used by the chip to detect dropped doorbells. The 57608 chip ID belonging to the P7 family is also defined. Note that the PCI ID is not added until the last patch in the series. Signed-off-by:
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Michael Chan authored
This updated interface supports the new 5760X P7 chip family. It has the changes to support the new link speeds/modes and other changes for the basic L2 features. Signed-off-by:
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Michael Chan authored
The current code determines the last backing store valid type during bnxt_hwrm_func_backing_store_qcaps_v2(). In effect, the last type is determined based on what firmware advertises. The more correct way is to determine it based on what the driver is configuring. The driver may not configure all the backing store types advertised by firmware. Move the logic to determine the last type to bnxt_backing_store_cfg_v2(). We need to pass the legacy enable flags to the function in case only the legacy types are being configured. Fixes: 236e237f ("bnxt_en: Add support for HWRM_FUNC_BACKING_STORE_CFG_V2 firmware calls") Signed-off-by:
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Guillaume Nault authored
Walk the hashinfo->bhash2 table so that inet_diag can dump TCP sockets that are bound but haven't yet called connect() or listen(). The code is inspired by the ->lhash2 loop. However there's no manual test of the source port, since this kind of filtering is already handled by inet_diag_bc_sk(). Also, a maximum of 16 sockets are dumped at a time, to avoid running with bh disabled for too long. There's no TCP state for bound but otherwise inactive sockets. Such sockets normally map to TCP_CLOSE. However, "ss -l", which is supposed to only dump listening sockets, actually requests the kernel to dump sockets in either the TCP_LISTEN or TCP_CLOSE states. To avoid dumping bound-only sockets with "ss -l", we therefore need to define a new pseudo-state (TCP_BOUND_INACTIVE) that user space will be able to set explicitly. With an IPv4, an IPv6 and an IPv6-only socket, bound respectively to 40000, 64000, 60000, an updated version of iproute2 could work as follow: $ ss -t state bound-inactive Recv-Q Send-Q Local Address:Port Peer Address:Port Process 0 0 0.0.0.0:40000 0.0.0.0:* 0 0 [::]:60000 [::]:* 0 0 *:64000 *:* Reviewed-by:
Eric Dumazet <edumazet@google.com> Signed-off-by:
Guillaume Nault <gnault@redhat.com> Reviewed-by:
Kuniyuki Iwashima <kuniyu@amazon.com> Link: https://lore.kernel.org/r/b3a84ae61e19c06806eea9c602b3b66e8f0cfc81.1701362867.git.gnault@redhat.comSigned-off-by:
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Jakub Kicinski authored
Heiko Stuebner says: ==================== net: phy: micrel: additional clock handling Some Micrel phys define a specific rmii-ref clock (added in 2014) while the generic phy binding specifies an unnamed clock for ethernet phys. This allows Micrel phys to use both, so as to keep the phys not using the named rmii-ref clock to conform to the generic binding while allowing them to enable a supplying clock, when the phy is not supplied by a dedicated oscillator. ==================== Link: https://lore.kernel.org/r/20231201150131.326766-1-heiko@sntech.deSigned-off-by:
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Heiko Stuebner authored
The generic ethernet-phy binding allows describing an external clock since commit 350b7a25 ("dt-bindings: net: phy: Document support for external PHY clk") for cases where the phy is not supplied by an oscillator but instead by a clock from the host system. And the old named "rmii-ref" clock from 2014 is only specified for phys of the KSZ8021, KSZ8031, KSZ8081, KSZ8091 types. So allow retrieving and enabling the optional generic clock on phys that do not provide a rmii-ref clock. Signed-off-by:
Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by:
Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20231201150131.326766-3-heiko@sntech.deSigned-off-by:
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Heiko Stuebner authored
While the external clock input will most likely be enabled, it's not guaranteed and clk_get_rate in some suppliers will even just return valid results when the clock is running. So use devm_clk_get_optional_enabled to retrieve and enable the clock in one go. Signed-off-by:
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Jiri Pirko authored
In case NLMSG_DONE message is sent as a reply to doit action, multiple kernel implementation do not send anything else than struct nlmsghdr. Add this note to the Netlink intro documentation. Signed-off-by:
Jiri Pirko <jiri@nvidia.com> Reviewed-by:
Bagas Sanjaya <bagasdotme@gmail.com> Link: https://lore.kernel.org/r/20231201180154.864007-1-jiri@resnulli.usSigned-off-by:
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David S. Miller authored
Suman Ghosh says: ==================== octeontx2: Multicast/mirror offload changes This patchset includes changes to support TC multicast/mirror offload. Patch #1: Adds changes to support new mailbox to offload multicast/mirror offload. Patch #2: Adds TC related changes which uses the newly added mailboxes to offload multicast/mirror rules. ==================== Signed-off-by:David S. Miller <davem@davemloft.net>
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Suman Ghosh authored
This patch extends TC flower offload support for mirroring ingress traffic to a different PF/VF. Below is an example command, 'tc filter add dev eth1 ingress protocol ip flower src_ip <ip-addr> skip_sw action mirred ingress mirror dev eth2' Signed-off-by:
Suman Ghosh <sumang@marvell.com> Reviewed-by:
Wojciech Drewek <wojciech.drewek@intel.com> Reviewed-by:
Simon Horman <horms@kernel.org> Signed-off-by:
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Suman Ghosh authored
A new mailbox is added to support offloading of multicast/mirror functionality. The mailbox also supports dynamic updation of the multicast/mirror list. Signed-off-by:
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- 02 Dec, 2023 9 commits
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David S. Miller authored
Coco Li says: ==================== Analyze and Reorganize core Networking Structs to optimize cacheline consumption Currently, variable-heavy structs in the networking stack is organized chronologically, logically and sometimes by cacheline access. This patch series attempts to reorganize the core networking stack variables to minimize cacheline consumption during the phase of data transfer. Specifically, we looked at the TCP/IP stack and the fast path definition in TCP. For documentation purposes, we also added new files for each core data structure we considered, although not all ended up being modified due to the amount of existing cacheline they span in the fast path. In the documentation, we recorded all variables we identified on the fast path and the reasons. We also hope that in the future when variables are added/modified, the document can be referred to and updated accordingly to reflect the latest variable organization. Tested: Our tests were run with neper tcp_rr using tcp traffic. The tests have $cpu number of threads and variable number of flows (see below). Tests were run on 6.5-rc1 Efficiency is computed as cpu seconds / throughput (one tcp_rr round trip). The following result shows efficiency delta before and after the patch series is applied. On AMD platforms with 100Gb/s NIC and 256Mb L3 cache: IPv4 Flows with patches clean kernel Percent reduction 30k 0.0001736538065 0.0002741191042 -36.65% 20k 0.0001583661752 0.0002712559158 -41.62% 10k 0.0001639148817 0.0002951800751 -44.47% 5k 0.0001859683866 0.0003320642536 -44.00% 1k 0.0002035190546 0.0003152056382 -35.43% IPv6 Flows with patches clean kernel Percent reduction 30k 0.000202535503 0.0003275329163 -38.16% 20k 0.0002020654777 0.0003411304786 -40.77% 10k 0.0002122427035 0.0003803674705 -44.20% 5k 0.0002348776729 0.0004030403953 -41.72% 1k 0.0002237384583 0.0002813646157 -20.48% On Intel platforms with 200Gb/s NIC and 105Mb L3 cache: IPv6 Flows with patches clean kernel Percent reduction 30k 0.0006296537873 0.0006370427753 -1.16% 20k 0.0003451029365 0.0003628016076 -4.88% 10k 0.0003187646958 0.0003346835645 -4.76% 5k 0.0002954676348 0.000311807592 -5.24% 1k 0.0001909169342 0.0001848069709 3.31% v8 changes: 1. Update net_device_read_txrx cache group maximum 2. Update MAINTAINERS for documentations 3. Skip __cache_group variables in scripts/kernel-doc ==================== Signed-off-by: -
Coco Li authored
Reorganize fast path variables on tx-txrx-rx order. Fastpath cacheline ends after sysctl_tcp_rmem. There are only read-only variables here. (write is on the control path and not considered in this case) Below data generated with pahole on x86 architecture. Fast path variables span cache lines before change: 4 Fast path variables span cache lines after change: 2 Suggested-by:
Wei Wang <weiwan@google.com> Reviewed-by:
David Ahern <dsahern@kernel.org> Signed-off-by:
Coco Li <lixiaoyan@google.com> Reviewed-by:
Shakeel Butt <shakeelb@google.com> Signed-off-by:
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Coco Li authored
Set up build time warnings to safeguard against future header changes of organized structs. Warning includes: 1) whether all variables are still in the same cache group 2) whether all the cache groups have the sum of the members size (in the maximum condition, including all members defined in configs) The __cache_group* variables are ignored in kernel-doc check in the various header files they appear in to enforce the cache groups. Suggested-by:
Daniel Borkmann <daniel@iogearbox.net> Acked-by:
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Coco Li authored
Analyzed a few structs in the networking stack by looking at variables within them that are used in the TCP/IP fast path. Fast path is defined as TCP path where data is transferred from sender to receiver unidirectionally. It doesn't include phases other than TCP_ESTABLISHED, nor does it look at error paths. We hope to re-organizing variables that span many cachelines whose fast path variables are also spread out, and this document can help future developers keep networking fast path cachelines small. Optimized_cacheline field is computed as (Fastpath_Bytes/L3_cacheline_size_x86), and not the actual organized results (see patches to come for these). Investigation is done on 6.5 Name Struct_Cachelines Cur_fastpath_cache Fastpath_Bytes Optimized_cacheline tcp_sock 42 (2664 Bytes) 12 396 8 net_device 39 (2240 bytes) 12 234 4 inet_sock 15 (960 bytes) 14 922 14 Inet_connection_sock 22 (1368 bytes) 18 1166 18 Netns_ipv4 (sysctls) 12 (768 bytes) 4 77 2 linux_mib 16 (1060) 6 104 2 Note how there isn't much improvement space for inet_sock and Inet_connection_sock because sk and icsk_inet respectively takes up so much of the struct that rest of the variables become a small portion of the struct size. So, we decided to reorganize tcp_sock, net_device, netns_ipv4 Suggested-by:
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Yinjun Zhang authored
NFP always supports software time stamping of tx, now expose the capability through ethtool ops. Signed-off-by:
Yinjun Zhang <yinjun.zhang@corigine.com> Signed-off-by:
Louis Peens <louis.peens@corigine.com> Link: https://lore.kernel.org/r/20231129080413.83789-1-louis.peens@corigine.comSigned-off-by:
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Niklas Söderlund authored
When breaking out the Gen4 gPTP support to its own module the dependency on the PTP_1588_CLOCK framework was left as optional and only stated for the driver using the module. This leads to issues when doing COMPILE_TEST of RENESAS_GEN4_PTP separately and PTP_1588_CLOCK is built as a module and the other as a built-in. Add an explicit depend on PTP_1588_CLOCK. While at it remove the optional support for PTP_1588_CLOCK from RENESAS_ETHER_SWITCH as the driver unconditionally calls the Gen4 gPTP module and thus also requires the PTP_1588_CLOCK framework. Reported-by:
Arnd Bergmann <arnd@arndb.de> Fixes: 8c1c6623 ("net: ethernet: renesas: rcar_gen4_ptp: Break out to module") Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
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Neil Armstrong authored
Document the IPA on the SM8650 Platform which uses version 5.5.1, which is a minor revision of v5.5 found on SM8550, thus we can use the SM8550 bindings as fallback since it shares the same register mappings. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231129-topic-sm8650-upstream-bindings-ipa-v1-1-ca21eb2dfb14@linaro.orgSigned-off-by:
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Nithin Dabilpuram authored
This patch update the CQ structure fields to support the feature added in new silicons and also dump these fields in debugfs. Signed-off-by:
Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by:
Geetha sowjanya <gakula@marvell.com> Link: https://lore.kernel.org/r/20231130060703.16769-1-gakula@marvell.comSigned-off-by:
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Maxime Chevallier authored
Physical Layer Collision Avoidance messages are correctly documented but were left-out of the global list of ethnl messages, add them to the list. Signed-off-by:
Maxime Chevallier <maxime.chevallier@bootlin.com> Link: https://lore.kernel.org/r/20231130191400.817948-1-maxime.chevallier@bootlin.comSigned-off-by:
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