1. 19 Mar, 2014 7 commits
  2. 13 Mar, 2014 3 commits
  3. 27 Feb, 2014 6 commits
    • Mike Turquette's avatar
      Merge branch 'clk-fixes' into clk-next · 5ba8dac0
      Mike Turquette authored
      5ba8dac0
    • Tomi Valkeinen's avatar
      clk: ti/divider: fix rate calculation for fractional rates · 7e50e7e1
      Tomi Valkeinen authored
      ti/clk-divider.c does not calculate the rates consistently at the moment.
      
      As an example, on OMAP3 we have a clock divider with a source clock of
      864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are:
      
      6: 144000000
      7: 123428571.428571...
      8: 108000000
      
      Calling clk_round_rate() with the rate in the first column will give the
      rate in the second column:
      
      144000000 -> 144000000
      143999999 -> 123428571
      123428572 -> 123428571
      123428571 -> 108000000
      
      Note how clk_round_rate() returns 123428571 for rates from 123428572 to
      143999999, which is mathematically correct, but when clk_round_rate() is
      called with 123428571, the returned value is surprisingly 108000000.
      
      This means that the following code works a bit oddly:
      
      rate = clk_round_rate(clk, 123428572);
      clk_set_rate(clk, rate);
      
      As clk_set_rate() also does clock rate rounding, the result is that the
      clock is set to the rate of 108000000, not 123428571 returned by the
      clk_round_rate.
      
      This patch changes the ti/clk-divider.c to use DIV_ROUND_UP when
      calculating the rate. This gives the following behavior which fixes the
      inconsistency:
      
      144000000 -> 144000000
      143999999 -> 123428572
      123428572 -> 123428572
      123428571 -> 108000000
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      7e50e7e1
    • Tomi Valkeinen's avatar
      clk: divider: fix rate calculation for fractional rates · b11d282d
      Tomi Valkeinen authored
      clk-divider.c does not calculate the rates consistently at the moment.
      
      As an example, on OMAP3 we have a clock divider with a source clock of
      864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are:
      
      6: 144000000
      7: 123428571.428571...
      8: 108000000
      
      Calling clk_round_rate() with the rate in the first column will give the
      rate in the second column:
      
      144000000 -> 144000000
      143999999 -> 123428571
      123428572 -> 123428571
      123428571 -> 108000000
      
      Note how clk_round_rate() returns 123428571 for rates from 123428572 to
      143999999, which is mathematically correct, but when clk_round_rate() is
      called with 123428571, the returned value is surprisingly 108000000.
      
      This means that the following code works a bit oddly:
      
      rate = clk_round_rate(clk, 123428572);
      clk_set_rate(clk, rate);
      
      As clk_set_rate() also does clock rate rounding, the result is that the
      clock is set to the rate of 108000000, not 123428571 returned by the
      clk_round_rate.
      
      This patch changes the clk-divider.c to use DIV_ROUND_UP when
      calculating the rate. This gives the following behavior which fixes the
      inconsistency:
      
      144000000 -> 144000000
      143999999 -> 123428572
      123428572 -> 123428572
      123428571 -> 108000000
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      b11d282d
    • Masanari Iida's avatar
      clk:at91: Fix memory leak in of_at91_clk_master_setup() · f63fcc90
      Masanari Iida authored
      cppcheck detected following error
      [clk-master.c:245]: (error) Memory leak: characteristics
      
      The original code forgot to free characteristics when
      irq_of_parse_and_map() failed.
      Signed-off-by: default avatarMasanari Iida <standby24x7@gmail.com>
      Acked-by Boris BREZILLON <b.brezillon@overkiz.com>
      Acked-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      f63fcc90
    • Lars-Peter Clausen's avatar
      clk: axi-clkgen: Add support for v2 · 1887c3a6
      Lars-Peter Clausen authored
      This patch adds support for the new v2 version of the axi-clkgen core.
      Unfortunately the method of accessing the registers is quite different on v2,
      while the content still stays largely the same. So the patch adds a small
      abstraction layer which implements the specific read and write functions for v1
      and v2 in callback functions.
      Signed-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
      1887c3a6
    • Zhangfei Gao's avatar
      clk: hisilicon: add hi3620_mmc_clks · 62ac983b
      Zhangfei Gao authored
      Suggest by Arnd: abstract mmc tuning as clock behavior,
      also because different soc have different tuning method and registers.
      hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.
      Signed-off-by: default avatarZhangfei Gao <zhangfei.gao@linaro.org>
      Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      Acked-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
      62ac983b
  4. 26 Feb, 2014 3 commits
  5. 25 Feb, 2014 8 commits
  6. 24 Feb, 2014 8 commits
  7. 23 Feb, 2014 5 commits