- 30 Aug, 2022 40 commits
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Johan Hovold authored
Deprecate the PHY node 'clock-names' property which specified that the PIPE clock name should have a bogus "lane" suffix. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20220830112923.3725-22-johan+linaro@kernel.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Johan Hovold authored
Add the missing the description of the PHY-provider child node which was ignored when converting to DT schema. Fixes: ccf51c1c ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml") Reviewed-by:
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Johan Hovold authored
The QMP PHY DT schema is getting unwieldy. Break out the USB PHY binding in a separate file. Reviewed-by:
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Johan Hovold authored
Add the missing the description of the PHY-provider child node which was ignored when converting to DT schema. Fixes: ccf51c1c ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml") Reviewed-by:
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Johan Hovold authored
Add the missing optional power-domains property used by the SM8150 UFS QMP PHY to the binding. Fixes: fe75b0c4 ("arm64: dts: qcom: sm8150: Add ufs power-domain entries") Reviewed-by:
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Johan Hovold authored
Add the missing "qref" clock used by the SM8450 UFS QMP PHY to the binding. Note that the "qref" clock was added to sm8450.dtsi by commit 07fa917a ("arm64: dts: qcom: sm8450: add ufs nodes") but the binding was never updated to match. Fixes: e04121ba ("dt-bindings: phy: qcom,qmp: Add SM8450 UFS phy compatible") Reviewed-by:
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Johan Hovold authored
The QMP PHY DT schema is getting unwieldy. Break out the UFS PHY binding in a separate file. Add an example node based on a cleaned up version of sc8280xp.dtsi. Reviewed-by:
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Johan Hovold authored
Deprecate the PHY node 'clock-names' property which specified that the PIPE clock name should have a bogus "lane" suffix. Reviewed-by:
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Johan Hovold authored
Add the missing the description of the PHY-provider child node which was ignored when converting to DT schema. Fixes: ccf51c1c ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml") Reviewed-by:
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Johan Hovold authored
The QMP PHY DT schema is getting unwieldy. Break out the PCIe PHY binding in a separate file. Add an example node based on a cleaned up version of sm8250.dtsi. Reviewed-by:
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Johan Hovold authored
Deprecate the PHY node 'reset-names' property which specified that the reset name should have an unnecessary "lane" suffix. Reviewed-by:
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Johan Hovold authored
Deprecate the PHY node 'clock-names' property which specified that the PIPE clock name should have an unnecessary "lane" suffix. Reviewed-by:
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Johan Hovold authored
Add the missing the description of the PHY-provider child nodes which were ignored when converting to DT schema. Fixes: ccf51c1c ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml") Reviewed-by:
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Johan Hovold authored
The QMP PHY DT schema is getting unwieldy. Break out the odd-bird msm8996-qmp-pcie-phy which is the only QMP PHY that uses separate "per-lane" nodes. Add an example node based on a cleaned up version of msm8996.dtsi. Reviewed-by:
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Johan Hovold authored
Drop the redundant comment about child nodes being required that was copied from the old binding documentation. Acked-by:
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Johan Hovold authored
Clean up the example node somewhat by grouping consumer and provider properties in the child node. Acked-by:
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Johan Hovold authored
Clean up the remaining descriptions by using uppercase "PHY" consistently and dropping redundant information from the register descriptions. Acked-by:
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Johan Hovold authored
Fix the incorrect description of the child nodes which claimed that one node is required per lane rather than per PHY. Acked-by:
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Johan Hovold authored
Drop the redundant supply and clock descriptions which did not add much information beyond what can be inferred from the corresponding resource names. Reviewed-by:
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Johan Hovold authored
Sort the compatible strings alphabetically to make it easier to look up entries and add new ones. Acked-by:
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Johan Hovold authored
The QMP PHY wrapper node is not a clock provider so drop the bogus '#clock-cells' property that was added when converting to DT schema. Fixes: ccf51c1c ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml") Reviewed-by:
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Wolfram Sang authored
Follow the advice of the below link and prefer 'strscpy' in this subsystem. Conversion is 1:1 because the return value is not used. Generated by a coccinelle script. Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220818210056.7205-1-wsa+renesas@sang-engineering.comSigned-off-by:
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Bjorn Andersson authored
The SC8280P has two copies of an USB/DP compbo PHY, add support for this to the Qualcomm QMP PHY driver. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220810042303.3583194-5-bjorn.andersson@linaro.orgSigned-off-by:
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Bjorn Andersson authored
The SC8280XP platform has two instances of the 5nm USB3 UNI phy attached to the multi-port USB controller, add definition for these. Signed-off-by:
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Bjorn Andersson authored
The swing and pre-emphasis tables differ between different PHY versions, or perhaps between different platforms. In particular in order to introduce SC8280XP these tables needs to be replaced. Make it possible to specify these tables per PHY config. Signed-off-by:
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Bjorn Andersson authored
The SC8280XP platform has a pair of 5nm USB3 UNI phys and a pair of 5nm USB4/3/DP combo PHYs, add a compatible for these. Signed-off-by:
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Dmitry Baryshkov authored
Define configuration to be used by combo USB3 + DisplayPort phy on SDM845 SoC family. It closely follows sc7180, however like the main USB3 phy it uses the qmp_v3_usb3phy_cfg config. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Chanho Park authored
Below error is detected from dtbs_check. exynos7-ufs-phy is required symbol clocks otherwise only PLL ref clock is required. clock-names: ['ref_clk'] is too short Reported-by:
Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by:
Chanho Park <chanho61.park@samsung.com> Reviewed-by:
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Uwe Kleine-König authored
The single difference between returning 0 and returning an error code in a platform remove callback is that in the latter case the platform core emits a warning about the error being ignored. If reset_control_assert() fails there is already a warning, so suppress the more generic (and less helpful) by returning 0 in tegra_xusb_padctl_remove(). This is a preparation for making platform remove callbacks return void. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20220716145403.107703-1-u.kleine-koenig@pengutronix.deSigned-off-by:
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Rob Herring authored
In order to ensure only documented properties are present, node schemas must have unevaluatedProperties or additionalProperties set to false (typically). Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Konrad Dybcio authored
Add a compatible for the USB PHY on SM6375 Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by:
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Bjorn Andersson authored
The Qualcomm SC8280XP platform has a number of eDP and DP PHY instances, add support for these. Signed-off-by:
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Bjorn Andersson authored
The eDP phy can be used to drive either eDP or DP output, with some minor variations in some of the configuration and seemingly a need for implementing swing and pre_emphasis calibration. Introduce a config object, indicating if the phy is operating in eDP or DP mode and swing/pre-emphasis calibration to support this. Signed-off-by:
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Bjorn Andersson authored
The TRANSCIEVER_BIAS_EN, HIGHZ_DRVR_EN and PHY_CFG_1 registers are used for lane configuration, with the currently hard coded configuration being a mix of 2 and 4 lane (effectively 2-lane). Properly implement lane configuration for 1, 2 and 4 lanes. Signed-off-by:
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Bjorn Andersson authored
With multiple Displayport PHYs the hard coded clock names collides, generate unique clock names based on the device name instead. Signed-off-by:
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Bjorn Andersson authored
The Qualcomm SC8280XP platform has both eDP and DP PHYs, add compatibles for these. Signed-off-by:
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Roger Quadros authored
For J7200-SR2.0 and AM64 we don't model Common refclock divider as a clock divider as the divisor rate is fixed based on operating reference clock frequency. We just program the recommended value into the register. This simplifies the device tree and implementation a lot. Signed-off-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-8-rogerq@kernel.orgSigned-off-by:
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Roger Quadros authored
j7200-wiz-10g supports 2 reference clocks. However, the control bits for these clocks is in a separate register that sits in the System Control register space. Handle that register. Signed-off-by:
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Roger Quadros authored
ti,j7200-wiz-10g supports an additional reference clock. Add compatible and the additional clock. Cc: Rob Herring <robh@kernel.org> Signed-off-by:
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Roger Quadros authored
Mark "pll[0|1]-refclk", "refclk-dig" and "cmn-refclk1?-dig-div" as deprecated. The clock muxes are provided by the device driver so not required in device tree. Cc: Rob Herring <robh@kernel.org> Signed-off-by:
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