- 09 Jan, 2020 7 commits
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Mikita Lipski authored
Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not support virtual DPCD registers, but do support DSC. The DSC caps can be read from the physical aux, like in SST DSC. These hubs have many different DEVICE_IDs. Add a new quirk to detect this case. v2: Fix error when checking return of drm_dp_read_desc Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
David Francis <David.Francis@amd.com> Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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David Francis authored
Add drm_dp_mst_dsc_aux_for_port. To enable DSC, the DSC_ENABLED register might have to be written on the leaf port's DPCD, its parent's DPCD, or the MST manager's DPCD. This function finds the correct aux for the job. As part of this, add drm_dp_mst_is_virtual_dpcd. Virtual DPCD is a DP feature new in DP v1.4, which exposes certain DPCD registers on virtual ports. v2: Remember to unlock mutex on all paths v3: Refactor to match coding style and increase brevity v4: - Check DSC capable MST sink connected directly to the device. - Check branch's port_parent to be set Cc: Lyude Paul <lyude@redhat.com> Reviewed-by: -
David Francis authored
This field on drm_dp_mst_branch was never filled It is initialized to zero when the port is kzallocced. When a port is added to the list, increment num_ports, and when a port is removed from the list, decrement num_ports. v2: remember to decrement on port removal v3: don't explicitly init to 0 v4: move decrement of num_ports to unlink_port function Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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David Francis authored
Instead of having drm_dp_dpcd_read/write and drm_dp_mst_dpcd_read/write as entry points into the aux code, have drm_dp_dpcd_read/write handle both. This means that DRM drivers can make MST DPCD read/writes. v2: Fix spacing v3: Dump dpcd access on MST read/writes v4: Fix calling wrong function on DPCD write v5: delete deprecated include of drmP.h Reviewed-by:
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David Francis authored
As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating if FEC can be supported up to that point in the MST network. The bit is the first byte of the ENUM_PATH_RESOURCES ack reply, bottom-most bit (refer to section 2.11.9.4 of DP standard, v1.4) That value is needed for FEC and DSC support Store it on drm_dp_mst_port Reviewed-by:
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David Francis authored
With DSC, bpp can be fractional in multiples of 1/16. Change drm_dp_calc_pbn_mode to reflect this, adding a new parameter bool dsc. When this parameter is true, treat the bpp parameter as having units not of bits per pixel, but 1/16 of a bit per pixel v2: Don't add separate function for this v3: In the equation divide bpp by 16 as it is expected not to leave any remainder v4: Added DSC test parameters for selftest Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
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Felix Kuehling authored
Use filep->private_data to store a pointer to the kfd_process data structure. Take an extra reference for that, which gets released in the kfd_release callback. Check that the process calling kfd_ioctl is the same that opened the file descriptor. Return -EBADF if it's not, so that this error can be distinguished in user mode. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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- 07 Jan, 2020 33 commits
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Thomas Anderson authored
For high-res (8K) or HFR (4K120) displays, using uncompressed pixel formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the "interesting" modes would be disabled, leaving only low-res or low framerate modes. This change lowers the pixel encoding to 4:2:2 or 4:2:0 if the max TMDS clock is exceeded. Verified that 8K30 and 4K120 are now available and working with a Samsung Q900R over an HDMI 2.0b link from a Radeon 5700. Reviewed-by:
Thomas Anderson <thomasanderson@google.com> Signed-off-by:
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Xiaodong Yan authored
[Why] Some combined docks will always trigger CP_IRQ but there's nothing the driver needs to take care of, but the CP_IRQ breaks the original hdcp state and triggers the driver to restart the authentication. [How] Add the event type check before restart the authentication or resend the stream management Signed-off-by:
Xiaodong Yan <Xiaodong.Yan@amd.com> Reviewed-by:
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Michael Strauss authored
[WHY] Some monitors trigger HDCP2.x timeout after reinitializing (e.g. toggling HDR) by taking longer than expected to return h' (h prime) Previously the 200ms watchdog timer retry count would hit MAX_NUM_OF_ATTEMPTS (4), causing fallback to HDCP1.x [HOW] Adding a 1s delay after an h' watchdog timeout provides enough time for affected monitors to return h' in time without hitting MAX_NUM_OF_ATTEMPTS Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Jing Zhou authored
[why] Most DP/HDMI monitors need more time to response rx_validation request. [how] Add generic 1000ms delay. Signed-off-by:
Jing Zhou <Jing.Zhou@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
[Why] We are returning incorrect error code for validate h prime [How] Return the right Error code Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
[Why] PSP needs session ID to destroy a session, In the case where we fail create session we don't have a session ID [How] Set the session ID before returning Signed-off-by:
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Bhawanpreet Lakha authored
We are returning SUCCESS when hdcp_status != Success. Fix it. Signed-off-by:
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Wambui Karuga authored
list_for_each() can be replaced by the more concise list_for_each_entry() here for iteration over the lists. This change was reported by coccinelle. Signed-off-by:
Wambui Karuga <wambui.karugax@gmail.com> Signed-off-by:
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Wambui Karuga authored
As single statement conditionals do not need to be wrapped around braces, the unnecessary braces can be removed. Signed-off-by:
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Wambui Karuga authored
Remove unnecessary variable comparisions to true/false in if statements and check the value of the variable directly. Signed-off-by:
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Alex Deucher authored
This reverts commit 51bfac71. This causes stability issues on some raven boards. Revert for now until a proper fix is completed. Bug: https://gitlab.freedesktop.org/drm/amd/issues/934 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206017Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Put it on one line to avoid whitespace issues when printing in the log. Reviewed-by:
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Alex Deucher authored
Rather than open coding it. This also changes the free masks to better reflect the usage by other components. Acked-by:
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Alex Deucher authored
So it can be shared with newer GMC versions. Reviewed-by:
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John Clements authored
defined macros for repetitive for loops Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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John Clements authored
switch CE counter register access' to use SMN disable UMC indexing mode Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Evan Quan authored
Provided an unified entry point. And fixed the confusing that the API usage is conflict with what the naming implies. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
Guard the content consistence between the view of GPU and CPU during the table transferring. Signed-off-by:
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Evan Quan authored
With "dpm=0", there will be no DPM enabled. The code needs to be refined to support this. Signed-off-by:
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Evan Quan authored
By this, we can avoid to pass in the VRAM address on every table transferring. That puts extra unnecessary traffics on SMU on some cases(e.g. polling the amdgpu_pm_info sysfs interface). V2: document what the driver table is for and how it works Signed-off-by:
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Evan Quan authored
So that we do not need to allocate a piece of VRAM for it. This is a preparation for coming change which unifies the VRAM address for all driver tables interaction with SMU. Signed-off-by:
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Kevin Wang authored
add navi10 & navi14 pstate profiling clock value support. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Zhigang Luo authored
Signed-off-by:
Zhigang Luo <zhigang.luo@amd.com> Signed-off-by:
Jane Jian <jane.jian@amd.com> Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Zhigang Luo authored
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Zhigang Luo authored
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Zhigang Luo authored
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John Clements authored
enable GPU recovery in event of uncorrectable UMC error Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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John Clements authored
reduced duplicate code increased wait time for PSP BL readiness Signed-off-by:
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Kevin Wang authored
replace internal size macro with linux size macro Signed-off-by:
Tianci Yin <tianci.yin@amd.com> Signed-off-by:
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John Clements authored
iterate over all error counter registers in SMN space removed support error counter access via MMIO Reviewed-by:
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Evan Quan authored
This is to fit the latest SMC firmware and it's backward compatible. Signed-off-by:
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Jack Zhang authored
Under sriov and pp_onevf mode, 1.take resume instead of hw_init for smc recover to avoid potential memory leak. 2.add return condition inside smc resume function for sriov_pp_onevf_mode and pm_enabled param. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Acked-by:
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Jack Zhang authored
Before, initialization of smu ip block would be skipped for sriov ASICs. But if there's only one VF being used, guest driver should be able to dump some HW info such as clks, temperature,etc. To solve this, now after onevf mode is enabled, host driver will notify guest. If it's onevf mode, guest will do smu hw_init and skip some steps in normal smu hw_init flow because host driver has already done it for smu. With this fix, guest app can talk with smu and dump hw information from smu. v2: refine the logic for pm_enabled.Skip hw_init by not changing pm_enabled. v3: refine is_support_sw_smu and fix some indentation issue. Signed-off-by:
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