- 14 Dec, 2020 1 commit
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Anders Roxell authored
When building mips tinyconfig with clang the following warning show up: arch/mips/lib/uncached.c:45:6: warning: variable 'sp' is uninitialized when used here [-Wuninitialized] if (sp >= (long)CKSEG0 && sp < (long)CKSEG2) ^~ arch/mips/lib/uncached.c:40:18: note: initialize the variable 'sp' to silence this warning register long sp __asm__("$sp"); ^ = 0 1 warning generated. Rework to make an explicit inline move, instead of the non-standard use of specifying registers for local variables. This is what's written from the gcc-10 manual [1] about specifying registers for local variables: "6.47.5.2 Specifying Registers for Local Variables ................................................. [...] "The only supported use for this feature is to specify registers for input and output operands when calling Extended 'asm' (*note Extended Asm::). [...]". [1] https://docs.w3cub.com/gcc~10/local-register-variablesSigned-off-by:Anders Roxell <anders.roxell@linaro.org> Reported-by:
Nathan Chancellor <natechancellor@gmail.com> Reported-by:
Naresh Kamboju <naresh.kamboju@linaro.org> Reviewed-by:
Nick Desaulniers <ndesaulniers@google.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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- 05 Dec, 2020 2 commits
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Alexander Dahl authored
The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. Signed-off-by:
Alexander Dahl <post@lespocky.de> Signed-off-by:
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Jinyang He authored
Most platforms do not need to do synci instruction operations when synci_step is 0. But for example, the synci implementation on Loongson64 platform has some changes. On the one hand, it ensures that the memory access instructions have been completed. On the other hand, it guarantees that all prefetch instructions need to be fetched again. And its address information is useless. Thus, only one synci operation is required when synci_step is 0 on Loongson64 platform. I guess that some other platforms have similar implementations on synci, so add judgment conditions in `while` to ensure that at least all platforms perform synci operations once. For those platforms that do not need synci, they just do one more operation similar to nop. Signed-off-by:
Jinyang He <hejinyang@loongson.cn> Signed-off-by:
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- 04 Dec, 2020 6 commits
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Tiezhu Yang authored
In order to get more memblock configuration with memblock=debug in the boot cmdline, move memblock_dump_all() to the end of setup_arch(), this can help us to get dmi_setup() and resource_init() memblock info, at least for now. Signed-off-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by:
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Wei Li authored
Currently we won't migrate irqs when offline CPUs, which has been implemented on most architectures. That will lead to some devices work incorrectly if the bound cores are offline. While that can be easily supported by enabling GENERIC_IRQ_MIGRATION. But i don't pretty known the reason it was not supported on all MIPS platforms. This patch add the support for irq migration on MIPS CPS platform, and it's tested on the interAptiv processor. Signed-off-by:
Wei Li <liwei391@huawei.com> Signed-off-by:
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Alexander Sverdlin authored
Because check_kernel_sections_mem() does exactly this for all platforms. Signed-off-by:
Alexander Sverdlin <alexander.sverdlin@nokia.com> Signed-off-by:
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Alexander Sverdlin authored
Linux doesn't own the memory immediately after the kernel image. On Octeon bootloader places a shared structure right close after the kernel _end, refer to "struct cvmx_bootinfo *octeon_bootinfo" in cavium-octeon/setup.c. If check_kernel_sections_mem() rounds the PFNs up, first memblock_alloc() inside early_init_dt_alloc_memory_arch() <= device_tree_init() returns memory block overlapping with the above octeon_bootinfo structure, which is being overwritten afterwards. Fixes: a94e4f24 ("MIPS: init: Drop boot_mem_map") Signed-off-by:
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Xingxing Su authored
Enable gcov profiling of the entire kernel on mips. Required changes include disabling profiling for: * arch/kernel/boot/compressed: not linked to main kernel. Lightly tested on Loongson 3A3000 an 3A4000, seems to work as expected. without "GCOV_PROFILE := n" in compressed Makefile, build errors as follows: ... ld: arch/mips/boot/compressed/string.o:(.data+0x88): undefined reference to `__gcov_merge_add' ld: arch/mips/boot/compressed/string.o: in function `_GLOBAL__sub_I_00100_0_memcpy': string.c:(.text.startup+0x4): undefined reference to `__gcov_init' ld: arch/mips/boot/compressed/string.o: in function `_GLOBAL__sub_D_00100_1_memcpy': string.c:(.text.exit+0x0): undefined reference to `__gcov_exit' ... Signed-off-by:
Youling Tang <tangyouling@loongson.cn> Signed-off-by:
Xingxing Su <suxingxing@loongson.cn> Signed-off-by:
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Andrey Zhizhikin authored
Commit 7ecdea4a ("backlight: generic_bl: Remove this driver as it is unused") removed geenric_bl driver from the tree, together with corresponding config option. Remove BACKLIGHT_GENERIC config item from all MIPS configurations. Fixes: 7ecdea4a ("backlight: generic_bl: Remove this driver as it is unused") Signed-off-by:
Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Acked-by:
Daniel Thompson <daniel.thompson@linaro.org> Acked-by:
Sam Ravnborg <sam@ravnborg.org> Cc: Sam Ravnborg <sam@ravnborg.org> Signed-off-by:
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- 27 Nov, 2020 6 commits
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Jinyang He authored
Reserve memory from &_text to &_end. Otherwise if kernel address was modified, the memory range of start_pfn to kernel_start_pfn would be reserved. Then we could not use this range. Signed-off-by:
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Thomas Bogendoerfer authored
Function is_aligned_hugepage_range is no longer needed. Signed-off-by: -
Tiezhu Yang authored
After commit 9cce844a ("MIPS: CPU#0 is not hotpluggable"), c->hotpluggable is 0 for CPU 0 and it will not generate a control file in sysfs for this CPU: [root@linux loongson]# cat /sys/devices/system/cpu/cpu0/online cat: /sys/devices/system/cpu/cpu0/online: No such file or directory [root@linux loongson]# echo 0 > /sys/devices/system/cpu/cpu0/online bash: /sys/devices/system/cpu/cpu0/online: Permission denied So no need to check CPU 0 in {loongson3,bmips,octeon}_cpu_disable(), just remove them. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Qinglang Miao authored
kfree(dev) has been called inside put_device so anther kfree would cause a use-after-free bug/ Fixes: 8286ae03 ("MIPS: Add CDMM bus support") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Qinglang Miao <miaoqinglang@huawei.com> Acked-by:
Serge Semin <fancer.lancer@gmail.com> Signed-off-by:
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Jinyang He authored
Provide a weak plat_get_fdt() in relocate.c in case some platform enable USE_OF while plat_get_fdt() is useless. 1MB RELOCATION_TABLE_SIZE is small for Loongson64 because too many instructions should be relocated. 2MB is enough in present. Add KASLR support for Loongson64. KASLR(kernel address space layout randomization) To enable KASLR on Loongson64: First, make loongson3_defconfig. Then, enable CONFIG_RELOCATABLE and CONFIG_RANDOMIZE_BASE. Finally, compile the kernel. To test KASLR on Loongson64: Start machine with KASLR kernel. The first time: # cat /proc/iomem 00200000-0effffff : System RAM 02f30000-03895e9f : Kernel code 03895ea0-03bc7fff : Kernel data 03e30000-04f43f7f : Kernel bss The second time: # cat /proc/iomem 00200000-0effffff : System RAM 022f0000-02c55e9f : Kernel code 02c55ea0-02f87fff : Kernel data 031f0000-04303f7f : Kernel bss We see that code, data and bss sections become randomize. Signed-off-by:
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Jinyang He authored
Apply_r_mips_26_rel() relocates instructions like j, jal and etc. These instructions consist of 6bits function field and 26bits address field. The value of target_addr as follows, ================================================================= | high 4bits | low 28bits | ================================================================= |the high 4bits of this PC | the low 26bits of instructions << 2| ================================================================= Thus, loc_orig and log_new both need high 4bits rather than high 6bits. Signed-off-by:
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- 19 Nov, 2020 6 commits
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Tiezhu Yang authored
As the user manual and code comment said, Loongson-3 has 4-scache banks, while Loongson-2K has only 2 banks, so we should multiply the number of scache banks, this multiply operation should be done by c->scache.sets instead of scache_size, otherwise we will get the wrong scache size when execute lscpu. For example, the scache size should be 8192K instead of 2048K on the Loongson 3A3000 and 3A4000 platform, we can see the related info in the following boot message: [loongson@linux ~]$ dmesg | grep "Unified secondary cache" [ 0.000000] Unified secondary cache 8192kB 16-way, linesize 64 bytes. [ 4.061909] Unified secondary cache 8192kB 16-way, linesize 64 bytes. [ 4.125629] Unified secondary cache 8192kB 16-way, linesize 64 bytes. [ 4.188379] Unified secondary cache 8192kB 16-way, linesize 64 bytes. E.g. without this patch: [loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size 2048K 2048K 2048K 2048K [loongson@linux ~]$ lscpu | grep "L2 cache" L2 cache: 2048K With this patch: [loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size 8192K 8192K 8192K 8192K [loongson@linux ~]$ lscpu | grep "L2 cache" L2 cache: 8192K Signed-off-by:
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Tiezhu Yang authored
Since commit 02cf2119 ("Cleanup the mess in cpu_cache_init."), cpu_has_6k_cache and cpu_has_8k_cache have no user, r6k_cache_init() and r8k_cache_init() are not defined for over 15 years, just remove them. Signed-off-by:
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Thomas Bogendoerfer authored
Protection map difference between RIXI and non RIXI cpus is _PAGE_NO_EXEC and _PAGE_NO_READ usage. Both already take care of cpu_has_rixi while setting up the page bits. So we just need one setup of protection map and can drop the now unused (and broken for RIXI) PAGE_* defines. Signed-off-by: -
Thomas Bogendoerfer authored
Introduce helper macro to make lines shorter. Signed-off-by: -
Thomas Bogendoerfer authored
MIPS protection bits are setup during runtime so using defines like PAGE_SHARED ignores this runtime changes. Using vm_get_page_prot to get correct page protection fixes this. Signed-off-by: -
Thomas Bogendoerfer authored
MIPS protection bits are setup during runtime so using defines like PAGE_READONLY ignores these runtime changes. To fix this we simply use the page protection of the setup vma. Signed-off-by:
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- 17 Nov, 2020 14 commits
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Álvaro Fernández Rojas authored
BCM6318 SoCs have a reset controller for certain components. Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Álvaro Fernández Rojas authored
BCM63268 SoCs have a reset controller for certain components. Signed-off-by:
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Álvaro Fernández Rojas authored
BCM6368 SoCs have a reset controller for certain components. Signed-off-by:
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Álvaro Fernández Rojas authored
BCM6362 SoCs have a reset controller for certain components. Signed-off-by:
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Álvaro Fernández Rojas authored
BCM6358 SoCs have a reset controller for certain components. Signed-off-by:
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Álvaro Fernández Rojas authored
BCM6328 SoCs have a reset controller for certain components. Signed-off-by:
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Álvaro Fernández Rojas authored
Add support for resetting blocks through the Linux reset controller subsystem for BCM63xx SoCs. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
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Álvaro Fernández Rojas authored
Add device tree binding documentation for BCM6345 reset controller. Signed-off-by:
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Álvaro Fernández Rojas authored
This allows to add reset controllers support. Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
1.Refresh defconfig of CI20 to support OTG and RNG. 2.Refresh defconfig of CU1000-Neo to support OTG/RNG/OST/SC16IS752. 3.Refresh defconfig of CU1830-Neo to support OTG/DTRNG/OST/SC16IS752. Tested-by:
周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Tested by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780 Signed-off-by:
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by:
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周琰杰 (Zhou Yanjie) authored
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20. 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752 nodes for CU1000-Neo. 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752 nodes for CU1830-Neo. Tested-by:
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Thomas Bogendoerfer authored
Pull in mips-fixes to get memblock fix. - fix bug preventing booting on several platforms - fix for build error, when modules need has_transparent_hugepage - fix for memleak in alchemy clk setup Signed-off-by: -
Zhang Qilong authored
If the clk_register fails, we should free h before function returns to prevent memleak. Fixes: 47440229 ("MIPS: Alchemy: clock framework integration of onchip clocks") Reported-by:
Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by:
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Thomas Bogendoerfer authored
The loop over all memblocks works with PFNs and not physical addresses, so we need for_each_mem_pfn_range(). Fixes: b10d6bca ("arch, drivers: replace for_each_membock() with for_each_mem_range()") Signed-off-by:
Mike Rapoport <rppt@linux.ibm.com> Reviewed-by:
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- 12 Nov, 2020 5 commits
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Alexander Lobakin authored
Commit c3e2ee65 ("MIPS: generic: Add support for zboot") added support for self-extracting images to Generic MIPS. However, the intended way to boot Generic MIPS kernels is using FIT Images and UHI boot protocol, but currently there's no way to make self-extracting FIT Image (only legacy uzImages). Add a target for this named "vmlinuz.itb", which will consist of vmlinuz.bin and selected DT blobs. It will allow to have the advantages of both UHI and self-extracting images. Signed-off-by:
Alexander Lobakin <alobakin@pm.me> Acked-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
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Alexander Lobakin authored
1. All final targets like vmlinuz.{bin,ecoff,srec} etc. should reside in $(objtree)/arch/mips/boot, not in the root $(objtree) directory. The only file that should be left there is vmlinuz, similar to other architectures. 2. Add all the targets to $(targets) variable, so they'll be properly accounted by Kbuild. This also allows to remove redundant $(clean-files) (which were missing uzImage BTW). 3. Prefix all targets with $(obj)/$(objtree), depending on their locations. Misc: fix the identation of the 'STRIP' quiet message. Signed-off-by: -
Gregory CLEMENT authored
Add a device trees and FIT image support for the Microsemi Serval SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
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Gregory CLEMENT authored
Add a device trees and FIT image support for the Microsemi Jaguar2 SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by:
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Gregory CLEMENT authored
Luton now has already an u-boot port so let's build FIT images. Signed-off-by:
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