Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

Pull tegra clk driver changes from Thierry Reding:

This set of changes contains a bunch of cleanups and minor fixes along
with some new clocks, mainly on Tegra210, in preparation for supporting
DisplayPort and HDMI 2.0.

* tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: dfll: Reformat CVB frequency table
  clk: tegra: dfll: Properly clean up on failure and removal
  clk: tegra: dfll: Make code more comprehensible
  clk: tegra: dfll: Reference CVB table instead of copying data
  clk: tegra: dfll: Update kerneldoc
  clk: tegra: Fix PLL_U post divider and initial rate on Tegra30
  clk: tegra: Initialize PLL_C to sane rate on Tegra30
  clk: tegra: Fix pllre Tegra210 and add pll_re_out1
  clk: tegra: Add sor_safe clock
  clk: tegra: dpaux and dpaux1 are fixed factor clocks
  clk: tegra: Add dpaux1 clock
  clk: tegra: Use correct parent for dpaux clock
  clk: tegra: Add fixed factor peripheral clock type
  clk: tegra: Special-case mipi-cal parent on Tegra114
  clk: tegra: Remove trailing blank line
  clk: tegra: Constify peripheral clock registers
  clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs

Merge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk updates from Heiko Stuebner:

A spelling fix and a bunch of rk3399 clock fixes.

* tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix the rk3399 cifout clock
  clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399
  clk: rockchip: add some frequencies on the rk3399 PLL table
  clk: rockchip: assign more necessary rk3399 clock ids
  clk: rockchip: export some necessary rk3399 clock ids
  clk: rockchip: rename rga clock-id on rk3399
  clk: rockchip: add general gpu soft-reset on rk3399
  clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
  clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type

Increase the readability of the CVB frequency table by reformatting it a
little.
Signed-off-by: Thierry Reding <treding@nvidia.com>

Upon failure to probe the DFLL, the OPP table will not be cleaned up
properly. Fix this and while at it make sure the OPP table will also be
cleared upon driver removal.
Signed-off-by: Thierry Reding <treding@nvidia.com>

Rename some variables and structure fields to make the code more
comprehensible. Also change the prototype of internal functions to be
more in line with the OPP core functions.
Signed-off-by: Thierry Reding <treding@nvidia.com>

Instead of copying parts of the CVB table into a separate structure,
keep track of the selected CVB table and directly reference data from
it.
Signed-off-by: Thierry Reding <treding@nvidia.com>

The kerneldoc for struct tegra_dfll_soc_data is stale. Update it to
match the current structure definition.
Signed-off-by: Thierry Reding <treding@nvidia.com>

The post divider value in the frequency table is wrong as it would lead
to the PLL producing an output rate of 960 MHz instead of the desired
480 MHz. This wasn't a problem as nothing used the table to actually
initialize the PLL rate, but the bootloader configuration was used
unaltered.

If the bootloader does not set up the PLL it will fail to come when used
under Linux. To fix this don't rely on the bootloader, but set the
correct rate in the clock driver.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>

If the bootloader does not touch PLL_C it will stay in its reset state,
failing to lock when enabled. This leads to consumers of this clock to
fail probing. Fix this by always programming the PLL with a sane rate,
which allows it to lock, at startup.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Use a new Tegra210 version of the pll_register_pllre function to
allow setting the proper settings for the m and n div fields.

Additionally define PLL_RE_OUT1 on Tegra210.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: define PLLRE_OUT1 register offset]
Signed-off-by: Thierry Reding <treding@nvidia.com>

The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.
Signed-off-by: Thierry Reding <treding@nvidia.com>

The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.
Signed-off-by: Thierry Reding <treding@nvidia.com>

This clock is of the same type as dpaux and is added to feed into the
second DPAUX block used in conjunction with SOR1.
Signed-off-by: Thierry Reding <treding@nvidia.com>

The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m.
Signed-off-by: Thierry Reding <treding@nvidia.com>

Some of the peripheral clocks on Tegra are derived from one of the top-
level PLLs with a fixed factor. Support these clocks by implementing the
->enable() and ->disable() callbacks using the peripheral clock register
banks and the ->recalc_rate() by dividing the parent rate by the fixed
factor.
Signed-off-by: Thierry Reding <treding@nvidia.com>

Starting with Tegra124, the mipi-cal clock uses the 72 MHz clock as its
source. On Tegra114 this clock's parent was clk_m, so it is the one-off
chip.
Signed-off-by: Thierry Reding <treding@nvidia.com>

Trailing blank lines are undesirable (several tools, such as git,
complain about them), so remove it.
Signed-off-by: Thierry Reding <treding@nvidia.com>

The peripheral clock registers are defined in static tables. These
tables never need to be modified at runtime, so they can reside in
read-only memory.
Signed-off-by: Thierry Reding <treding@nvidia.com>

On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE enable
sequence.  Export functions to do this so that hardware control can
be enabled from the XUSB padctl driver.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The cifout clock is incorrect due to the manual error, we need to
fix it.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

We don't need to many clocks enable after startup, to reduce some
power consumption.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch add some necessary frequencies for the RK3399 clock.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Assign newly added clock ids.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

We export some clock IDs for the reference drivers need them.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The rga clock supplying the working clock on the rk3399 is actually
called rga-core in the manual. As the clock id has neither been
assigned nor released with a full kernel release, we can still change
the id to the more appropriate naming.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add the id for the general gpu soft-reset, that got documented only in
newer TRM versions.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The gate bits of the i2c4 and i2c8 are incorrect due to the manual
error, we need to fix them.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

fix spelling mistake, unsucessful -> unsuccessful
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

* 'clk-hw-register' (early part):
  clk: fixed-rate: Add hw based registration APIs
  clk: gpio: Add hw based registration APIs
  clk: composite: Add hw based registration APIs
  clk: fractional-divider: Add hw based registration APIs
  clk: fixed-factor: Add hw based registration APIs
  clk: mux: Add hw based registration APIs
  clk: gate: Add hw based registration APIs
  clk: divider: Add hw based registration APIs
  clkdev: Add clk_hw based registration APIs
  clk: Add clk_hw OF clk providers
  clk: Add {devm_}clk_hw_{register,unregister}() APIs
  clkdev: Remove clk_register_clkdevs()

* clk-composite-unregister:
  clk: composite: Add unregister function

The composite clock didn't have any unregistration function, which forced
us to use clk_unregister directly on it.

While it was already not great from an API point of view, it also meant
that we were leaking the clk_composite structure allocated in
clk_register_composite.

Add a clk_unregister_composite function to fix this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[sboyd@codeaurora.org: Drop NULL/continue check in registration
loop]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Merge tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

clk: renesas: R-Car SYSC PM Domain Preparation

  - Export the CPG/MSSR and CPG/MSTP attach/detach_dev callbacks, so
    they can be called by the R-Car SYSC PM Domain driver.

* tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()
  clk: renesas: mstp: Provide dummy attach/detach_dev callbacks
  clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support

Merge tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull some checkpatch silencers from Heiko Stuebner:

Fix quite some checkpatch warnings in the newly added
rk3399 header and also in the clock code itself.

* tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix checkpatch warning in core code
  clk: rockchip: drop unnecessary header comment
  clk: rockchip: reign in some overly long lines in the rk3399 controller
  clk: rockchip: fix checkpatch errors in rk3399 dt-binding header

We seem to have accumulated a bunch of checkpatch warnings, with mainly
overlong lines and two unnecessary allocation error messages.
Most were introduced with the recent multi-controller-support but some
were quite a bit older.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The R-Car SYSC PM Domain driver has to power manage devices in power
areas using clocks. To reuse code and to share knowledge of clocks
suitable for power management, this is ideally done through the existing
cpg_mssr_attach_dev() and cpg_mssr_detach_dev() callbacks.

Hence these callbacks can no longer rely on their "domain" parameter
pointing to the CPG/MSSR Clock Domain. To handle this, keep a pointer to
the clock domain in a static variable. cpg_mssr_attach_dev() has to
support probe deferral, as the R-Car SYSC PM Domain may be initialized,
and devices may be added to it, before the CPG/MSSR Clock Domain is
initialized.

Dummy callbacks are provided for the case where CPG/MSTP support is not
included, so the rcar-sysc driver won't have to care about this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Provide dummy cpg_mstp_{at,de}tach_dev() PM Domain callbacks if CPG/MSTP
support is not included, so the rcar-sysc driver won't have to care
about this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Currently the decision whether to build the renesas-cpg-mssr and
clk-mstp drivers is handled by Makefile logic.  However, the rcar-sysc
driver will need to know whether CPG/MSSR and/or CPG/MSTP support are
available or not.

To avoid having to duplicate this logic, move it to Kconfig. Provide
non-visible CLK_RENESAS_CPG_MSSR and CLK_RENESAS_CPG_MSTP Kconfig
symbols, which can be used by both Makefiles and C code.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>