- 24 Oct, 2010 40 commits
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Avi Kivity authored
emulate_push() only schedules a push; it doesn't actually push anything. Call writeback() to flush out the write. Signed-off-by:Avi Kivity <avi@redhat.com>
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Wei Yongjun authored
Signed-off-by:
Wei Yongjun <yjwei@cn.fujitsu.com> Signed-off-by:
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Wei Yongjun authored
Change OUT instruction to use dst instead of src, so we can reuse those code for all out instructions. Signed-off-by:
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Wei Yongjun authored
Introduce DstImmUByte for dst operand decode, which will be used for out instruction. Signed-off-by:
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Wei Yongjun authored
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Wei Yongjun authored
Add setcc instruction emulation (opcode 0x0f 0x90~0x9f) Signed-off-by:
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Jiri Kosina authored
no-kvmclock kernel parameter is missing its explanation in Documentation/kernel-parameters.txt. Add it. Signed-off-by:
Jiri Kosina <jkosina@suse.cz> Signed-off-by:
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Wei Yongjun authored
Add XADD instruction emulation (opcode 0x0f 0xc0~0xc1) Signed-off-by:
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Wei Yongjun authored
Introduce function write_register_operand() to write back the register operand. Signed-off-by:
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Wei Yongjun authored
Add kvm_release_page_clean() after is_error_page() to avoid leakage of error page. Signed-off-by:
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Mohammed Gamal authored
The code for initializing the emulation context is duplicated at two locations (emulate_instruction() and kvm_task_switch()). Separate it in a separate function and call it from there. Signed-off-by:
Mohammed Gamal <m.gamal005@gmail.com> Signed-off-by:
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Wei Yongjun authored
Add bsf/bsr instruction emulation (opcode 0x0f 0xbc~0xbd) Signed-off-by:
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Mohammed Gamal authored
This patch lets emulate_grp3() return X86EMUL_* return codes instead of hardcoded ones. Signed-off-by:
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Mohammed Gamal authored
This adds unary mul, imul, div, and idiv instructions (group 3 r/m 4-7). Signed-off-by:
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Wei Yongjun authored
Mask group 8 instruction as BitOp, so we can share the code for adjust the source operand. Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com> Signed-off-by:
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Wei Yongjun authored
adjust the dst address for a register source but not adjust the address for an immediate source. Signed-off-by:
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Wei Yongjun authored
If bit offset operands is a negative number, BitOp instruction will return wrong value. This patch fix it. Signed-off-by:
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Mohammed Gamal authored
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Wei Yongjun authored
Using SrcOne for instruction d0/d1 decoding. Signed-off-by:
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Wei Yongjun authored
This patch change to disable writeback when decode dest operand if the dest type is ImplicitOps or not specified. Signed-off-by:
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Wei Yongjun authored
Use SrcAcc to simplify stos decoding. Signed-off-by:
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Mohammed Gamal authored
This adds support for int instructions to the emulator. Signed-off-by:
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Mohammed Gamal authored
The patch adds a new member get_idt() to x86_emulate_ops. It also adds a function to get the idt in order to be used by the emulator. This is needed for real mode interrupt injection and the emulation of int instructions. Signed-off-by:
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Wei Yongjun authored
Two-byte opcode always start with 0x0F and the decode flags of opcode 0xF0 is always 0, so remove dup check. Signed-off-by:
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Alexander Graf authored
When using a relocatable kernel we need to make sure that the trampline code and the interrupt handlers are both copied to low memory. The only way to do this reliably is to put them in the copied section. This patch should make relocated kernels work with KVM. KVM-Stable-Tag Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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Alexander Graf authored
On Book3S KVM we directly expose some asm pointers to C code as variables. These need to be relocated and thus break on relocatable kernels. To make sure we can at least build, let's mark them as long instead of u32 where 64bit relocations don't work. This fixes the following build error: WARNING: 2 bad relocations^M > c000000000008590 R_PPC64_ADDR32 .text+0x4000000000008460^M > c000000000008594 R_PPC64_ADDR32 .text+0x4000000000008598^M Please keep in mind that actually using KVM on a relocated kernel might still break. This only fixes the compile problem. Reported-by:
Subrata Modak <subrata@linux.vnet.ibm.com> Signed-off-by:
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Alexander Graf authored
Book3S_32 requires MSR_DR to be disabled during load_up_xxx while on Book3S_64 it's supposed to be enabled. I misread the code and disabled it in both cases, potentially breaking the PS3 which has a really small RMA. This patch makes KVM work on the PS3 again. Signed-off-by:
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Alexander Graf authored
On Book3s_32 the tlbie instruction flushed effective addresses by the mask 0x0ffff000. This is pretty hard to reflect with a hash that hashes ~0xfff, so to speed up that target we should also keep a special hash around for it. Signed-off-by:
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Gleb Natapov authored
On failure gfn_to_pfn returns bad_page so use correct function to check for that. Signed-off-by:
Gleb Natapov <gleb@redhat.com> Signed-off-by:
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Alexander Graf authored
So far we've been running all code without locking of any sort. This wasn't really an issue because I didn't see any parallel access to the shadow MMU code coming. But then I started to implement dirty bitmapping to MOL which has the video code in its own thread, so suddenly we had the dirty bitmap code run in parallel to the shadow mmu code. And with that came trouble. So I went ahead and made the MMU modifying functions as parallelizable as I could think of. I hope I didn't screw up too much RCU logic :-). If you know your way around RCU and locking and what needs to be done when, please take a look at this patch. Signed-off-by:
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Alexander Graf authored
Due to previous changes, the Book3S_32 guest MMU code didn't compile properly when enabling debugging. This patch repairs the broken code paths, making it possible to define DEBUG_MMU and friends again. Signed-off-by:
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Alexander Graf authored
We need to tell the guest the opcodes that make up a hypercall through interfaces that are controlled by userspace. So we need to add a call for userspace to allow it to query those opcodes so it can pass them on. This is required because the hypercall opcodes can change based on the hypervisor conditions. If we're running in hardware accelerated hypervisor mode, a hypercall looks different from when we're running without hardware acceleration. Signed-off-by:
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Alexander Graf authored
We just introduced a new PV interface that screams for documentation. So here it is - a shiny new and awesome text file describing the internal works of the PPC KVM paravirtual interface. Signed-off-by:
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Alexander Graf authored
On BookE the preferred way to write the EE bit is the wrteei instruction. It already encodes the EE bit in the instruction. So in order to get BookE some speedups as well, let's also PV'nize thati instruction. Signed-off-by:
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Alexander Graf authored
There is also a form of mtmsr where all bits need to be addressed. While the PPC64 Linux kernel behaves resonably well here, on PPC32 we do not have an L=1 form. It does mtmsr even for simple things like only changing EE. So we need to hook into that one as well and check for a mask of bits that we deem safe to change from within guest context. Signed-off-by:
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Alexander Graf authored
The PowerPC ISA has a special instruction for mtmsr that only changes the EE and RI bits, namely the L=1 form. Since that one is reasonably often occuring and simple to implement, let's go with this first. Writing EE=0 is always just a store. Doing EE=1 also requires us to check for pending interrupts and if necessary exit back to the hypervisor. Signed-off-by:
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Alexander Graf authored
When we hook an instruction we need to make sure we don't clobber any of the registers at that point. So we write them out to scratch space in the magic page. To make sure we don't fall into a race with another piece of hooked code, we need to disable interrupts. To make the later patches and code in general easier readable, let's introduce a set of defines that save and restore r30, r31 and cr. Let's also define some helpers to read the lower 32 bits of a 64 bit field on 32 bit systems. Signed-off-by:
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Alexander Graf authored
We will need to patch several instruction streams over to a different code path, so we need a way to patch a single instruction with a branch somewhere else. This patch adds a helper to facilitate this patching. Signed-off-by:
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Alexander Graf authored
We will soon require more sophisticated methods to replace single instructions with multiple instructions. We do that by branching to a memory region where we write replacement code for the instruction to. This region needs to be within 32 MB of the patched instruction though, because that's the furthest we can jump with immediate branches. So we keep 1MB of free space around in bss. After we're done initing we can just tell the mm system that the unused pages are free, but until then we have enough space to fit all our code in. Signed-off-by:
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Alexander Graf authored
With our current MMU scheme we don't need to know about the tlbsync instruction. So we can just nop it out. Signed-off-by:
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