1. 21 Jun, 2024 1 commit
  2. 20 Jun, 2024 3 commits
  3. 19 Jun, 2024 2 commits
    • Marc Kleine-Budde's avatar
      spi: spi-imx: imx51: revert burst length calculation back to bits_per_word · df75470b
      Marc Kleine-Budde authored
      The patch 15a6af94 ("spi: Increase imx51 ecspi burst length based
      on transfer length") increased the burst length calculation in
      mx51_ecspi_prepare_transfer() to be based on the transfer length.
      
      This breaks HW CS + SPI_CS_WORD support which was added in
      6e95b23a ("spi: imx: Implement support for CS_WORD") and transfers
      with bits-per-word != 8, 16, 32.
      
      SPI_CS_WORD means the CS should be toggled after each word. The
      implementation in the imx-spi driver relies on the fact that the HW CS
      is toggled automatically by the controller after each burst length
      number of bits. Setting the burst length to the number of bits of the
      _whole_ message breaks this use case.
      
      Further the patch 15a6af94 ("spi: Increase imx51 ecspi burst
      length based on transfer length") claims to optimize the transfers.
      But even without this patch, on modern spi-imx controllers with
      "dynamic_burst = true" (imx51, imx6 and newer), the transfers are
      already optimized, i.e. the burst length is dynamically adjusted in
      spi_imx_push() to avoid the pause between the SPI bursts. This has
      been confirmed by a scope measurement on an imx6d.
      
      Subsequent Patches tried to fix these and other problems:
      
      - 5f66db08 ("spi: imx: Take in account bits per word instead of assuming 8-bits")
      - e9b220ae ("spi: spi-imx: correctly configure burst length when using dma")
      - c712c05e ("spi: imx: fix the burst length at DMA mode and CPU mode")
      - cf6d79a0 ("spi: spi-imx: fix off-by-one in mx51 CPU mode burst length")
      
      but the HW CS + SPI_CS_WORD use case is still broken.
      
      To fix the problems revert the burst size calculation in
      mx51_ecspi_prepare_transfer() back to the original form, before
      15a6af94 ("spi: Increase imx51 ecspi burst length based on
      transfer length") was applied.
      
      Cc: Stefan Moring <stefan.moring@technolution.nl>
      Cc: Stefan Bigler <linux@bigler.io>
      Cc: Clark Wang <xiaoning.wang@nxp.com>
      Cc: Carlos Song <carlos.song@nxp.com>
      Cc: Sebastian Reichel <sre@kernel.org>
      Cc: Thorsten Scherer <T.Scherer@eckelmann.de>
      Fixes: 15a6af94 ("spi: Increase imx51 ecspi burst length based on transfer length")
      Fixes: 5f66db08 ("spi: imx: Take in account bits per word instead of assuming 8-bits")
      Fixes: e9b220ae ("spi: spi-imx: correctly configure burst length when using dma")
      Fixes: c712c05e ("spi: imx: fix the burst length at DMA mode and CPU mode")
      Fixes: cf6d79a0 ("spi: spi-imx: fix off-by-one in mx51 CPU mode burst length")
      Link: https://lore.kernel.org/all/20240618-oxpecker-of-ideal-mastery-db59f8-mkl@pengutronix.deSigned-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
      Tested-by: default avatarThorsten Scherer <t.scherer@eckelmann.de>
      Link: https://msgid.link/r/20240618-spi-imx-fix-bustlength-v1-1-2053dd5fdf87@pengutronix.deSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      df75470b
    • Amit Kumar Mahapatra's avatar
      spi: spi-cadence: Enable spi refclk in slave mode · 78b05172
      Amit Kumar Mahapatra authored
      When spi-cadence is configured as a slave, it requires the SPI refclk to
      detect the synchronization start condition while communicating with the
      master. However, the spi-cadence driver never enables the SPI refclk in
      slave mode, causing the refclk to remain disabled if the
      "clk_ignore_unused" kernel parameter is not passed through bootargs.
      As a result, the slave cannot detect data sent by the master, leading to
      communication failure. Update driver to enable the SPI refclk in both
      master and slave configurations.
      
      Fixes: b1b90514 ("spi: spi-cadence: Add support for Slave mode")
      Signed-off-by: default avatarAmit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
      Link: https://msgid.link/r/20240617153837.29861-1-amit.kumar-mahapatra@amd.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      78b05172
  4. 18 Jun, 2024 5 commits
  5. 12 Jun, 2024 1 commit
  6. 11 Jun, 2024 1 commit
    • Mark Brown's avatar
      spi: Rework DMA mapped flag · 412a05d6
      Mark Brown authored
      Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>:
      
      The first part of the series (patches 1 to 7) is an introduction
      of a new helper followed by the user conversion.
      
      This consolidates the same code and also makes patch 8 (last one)
      be localised to the SPI core part.
      
      The last patch is the main rework to get rid of a recently introduced
      hack with a dummy SG list and move to the transfer-based DMA mapped
      flag.
      
      That said, the patches 1 to 7 may be applied right away since they
      have no functional change intended, while the last one needs more
      testing and reviewing.
      412a05d6
  7. 10 Jun, 2024 10 commits
  8. 07 Jun, 2024 1 commit
  9. 05 Jun, 2024 2 commits
  10. 04 Jun, 2024 1 commit
  11. 03 Jun, 2024 12 commits
  12. 02 Jun, 2024 1 commit