- 21 Jun, 2022 13 commits
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Cruise Hung authored
Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Cruise Hung <Cruise.Hung@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yifan Zhang authored
This patch adds LSDMA ip block for LSDMA v6.0.1. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why&How] The omitted register definition caused call traces like: [ 3.811215] WARNING: CPU: 7 PID: 794 at drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.c:120 set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu] [ 3.811406] Modules linked in: amdgpu(+) drm_ttm_helper ttm iommu_v2 gpu_sched drm_kms_helper cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea drm i2c_piix4 drm_panel_orientation_quirks [ 3.811419] CPU: 7 PID: 794 Comm: systemd-udevd Not tainted 5.16.0-kfd+ #132 [ 3.811422] Hardware name: System manufacturer System Product Name/ROG STRIX B450-F GAMING, BIOS 3003 12/09/2019 [ 3.811425] RIP: 0010:set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu] [ 3.811615] Code: 08 49 89 51 08 8b 08 48 8d 42 08 49 89 41 08 44 8b 02 48 8d 50 08 0f b6 c9 49 89 51 08 8b 00 45 85 c0 75 b3 0f 0b eb af 5d c3 <0f> 0b e9 48 ff ff ff 49 8b 51 08 eb d0 49 8b 41 08 eb d5 66 0f 1f [ 3.811619] RSP: 0018:ffffb8c1c04cf640 EFLAGS: 00010246 [ 3.811621] RAX: 0000000000000000 RBX: ffff96f2100d8800 RCX: 0000000000000000 [ 3.811623] RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffffb8c1c04cf650 [ 3.811625] RBP: ffffb8c1c04cf640 R08: 000000000000047f R09: ffffb8c1c04cf658 [ 3.811627] R10: ffff96f5161ff000 R11: ffff96f5161ff000 R12: ffff96f204afb9c0 [ 3.811629] R13: 0000000000000000 R14: ffff96f202b94c00 R15: ffffb8c1c04cf718 [ 3.811631] FS: 00007fe07c2e2880(0000) GS:ffff96f5059c0000(0000) knlGS:0000000000000000 [ 3.811634] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3.811636] CR2: 0000559634ab57b8 CR3: 0000000120674000 CR4: 00000000003506e0 [ 3.811637] Call Trace: [ 3.811640] <TASK> [ 3.811642] generic_reg_update_ex+0x69/0x200 [amdgpu] [ 3.811831] ? _printk+0x58/0x6f [ 3.811836] dcn32_init_crb+0x18f/0x1b0 [amdgpu] [ 3.812031] dcn32_init_hw+0x379/0x6a0 [amdgpu] [ 3.812223] dc_hardware_init+0xba/0x100 [amdgpu] [ 3.812415] amdgpu_dm_init.isra.0.cold+0x166/0x1867 [amdgpu] [ 3.812616] ? dev_vprintk_emit+0x139/0x15d [ 3.812621] ? dev_printk_emit+0x4e/0x65 [ 3.812624] dm_hw_init+0x12/0x30 [amdgpu] [ 3.812820] amdgpu_device_init.cold+0x130d/0x178c [amdgpu] [ 3.813017] ? pci_read_config_word+0x25/0x40 [ 3.813021] amdgpu_driver_load_kms+0x1a/0x130 [amdgpu] [ 3.813178] amdgpu_pci_probe+0x130/0x330 [amdgpu] Fixes: 4f29f9cf ("drm/amd: add register headers for DCN32/321") Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
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Mario Limonciello authored
Some APUs with SMU13 are showing the following message: `amdgpu 0000:63:00.0: amdgpu: Unexpected and unhandled version: 3.1` This warning isn't relevant for smu info 3.1, as no bootup information is present in the table. Fixes: 593a54f1 ("drm/amd/pm: correct the way for retrieving bootup clocks") Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Yang Wang authored
set mp1 unload state will cause the SMC FW can't accept any SMU message, skip to set mp1 unload state to avoid following case fail: - runtime pm case. - gpu reset case. Fixes: 72aeb6ee ("drm/amd/pm: fix driver reload SMC firmware fail issue for smu13") Signed-off-by:
Yang Wang <KevinYang.Wang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Jack Xiao authored
Due to gfxoff on, cpu accessing registers is not expected. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Stanley.Yang authored
The EccInfo_t struct in driver_if.h is as below in official release verion 68.55.0 typedef struct { uint64_t mca_umc_status; uint64_t mca_umc_addr; uint16_t ce_count_lo_chip; uint16_t ce_count_hi_chip; uint32_t eccPadding; uint64_t mca_ceumc_addr; } EccInfo_t; It's different from the debug version druing develop print correctable error address, so adjust EccInfo_t struct. Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Alex Deucher authored
Certain GL unit tests for large textures can cause problems with the OOM killer since there is no way to link this memory to a process. This was originally mitigated (but not necessarily eliminated) by limiting the GTT size. The problem is this limit is often too low for many modern games so just make the limit 1/2 of system memory. The OOM accounting needs to be addressed, but we shouldn't prevent common 3D applications from being usable just to potentially mitigate that corner case. Set default GTT size to max(3G, 1/2 of system ram) by default. v2: drop previous logic and default to 3/4 of ram v3: default to half of ram to align with ttm v4: fix spelling in comment (Kent) Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1942Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Alex Deucher authored
radeon is MIT. This were incorrectly changed in commit b2441318 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") and commit d198b34f (".gitignore: add SPDX License Identifier") and: commit ec8f24b7 ("treewide: Add SPDX license identifier - Makefile/Kconfig") Fixes: d198b34f (".gitignore: add SPDX License Identifier") Fixes: ec8f24b7 ("treewide: Add SPDX license identifier - Makefile/Kconfig") Fixes: b2441318 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2053Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Graham Sider authored
Loop through all VMIDs for gmc_v10_0_flush_gpu_tlb_pasid and gmc_v11_0_flush_gpu_tlb_pasid (only if using MES for gmc_v10). This is required for MES due to use_different_vmid_compute causing SDMA queues to be assigned different VMIDs than compute for the same PASID. Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Ruijing Dong authored
Fixed some errors and warnings found by checkpatch.pl. Acked-by:
Ruijing Dong <ruijing.dong@amd.com> Signed-off-by:
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Ruijing Dong authored
- remove multiple queue support - add unified queue related functions Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Ruijing Dong authored
- add unified queue headers - add unified queue ib tests Acked-by:
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- 15 Jun, 2022 27 commits
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Rodrigo Siqueira authored
Signed-off-by:
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Alex Deucher authored
Use the same pattern as the DML Makefile and while we are here add a missing x86 guard around the msse flags for DCN3.2.x. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
This reverts commit d8e4fb91. This is no longer necessary as newer patches require these functions without CONFIG_DRM_AMD_DC_DCN. Reviewed-by:
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Alex Deucher authored
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1542:11: warning: variable 'i' set but not used [-Wunused-but-set-variable] Reviewed-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Yifan Zhang authored
enable_mes and enable_mes_kiq are set in both device init and MES IP init. Leave the ones in MES IP init, since it is a more accurate way to judge from GC IP version. Signed-off-by:
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Joshua Aberback authored
[Why] All displays need to be blanked during the uclk OC interface so that we can guarantee pstate switching support. If the display config doesn't support pstate switching, only using core_link_disable_stream will not enable it as the front-end is untouched. We need to go through the full plane removal sequence to properly program the pipe to allow pstate switching. [How] - guard clk_mgr functions with non-NULL checks Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Tested-by:
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Martin Leung authored
[why] dc_submit_i2c_oem could be called with ddc null [how] add null check and fail the call instead Acked-by:
Martin Leung <martin.leung@amd.com> Tested-by:
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Charlene Liu authored
[why] need to add timing adjustment for fva. [how] add hook to optc and hwseq. Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Harry VanZyllDeJong authored
[WHY] The display driver on some OSes need to track it in order to perform memory clock switching decisions. [HOW] Propagate the vrr active state to dirty bit so that on mode set it disables dynamic memory clock switching. Acked-by:
Harry VanZyllDeJong <harry.vanzylldejong@amd.com> Tested-by:
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Felipe Clark authored
[WHY] New features will require knowing the vrr mode for their enablement. [HOW] Pass the state via a member of dc_stream. Acked-by:
Felipe Clark <Felipe.Clark@amd.com> Tested-by:
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Ahmad Othman authored
[Why] Video Timing Extended Metadata packet (VTEM) is required for features like VRR and FVA [How] Adding support for VTEM transmission to stream encoders in DCN20 and DCN30 as part of FVA support Acked-by:
Ahmad Othman <ahmad.othman@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why & How] Miss to copy hfvsif_infopacket when copying stream updates. Check and copy it. Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Ahmad Othman authored
[Why] - Currently there is no support for HF-VSIF - The current support of VSIF is limited to H14b infoframe [How] - refactor VSIF - Added new builder for HF-VSIF - Added the HF-VSIF packet to DisplayTarget - Updates DC to apply HF-VSIF updates when updating streams Acked-by:
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Felipe Clark authored
[WHY] Memory clock switching has great potential for power savings. [HOW] The driver code was modified to notify the DMCUB firmware that it should stretch the vertical blank of frames when a memory clock switch is about to start so that no blackouts happen on the screen due to unavailability of the frame buffer. The driver logic to determine when such firmware assisted strategy can be initiated is also implemented and consists on checking prerequisites of the feature. Acked-by:
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Ian Chen authored
[Why] - missing in dcn30 function - Fix a divide by 0 when ACR trigger [How] - Add IS_SMU_TIMEOUT() to dcn30_smu_send_msg_with_param - Add zero check in dcn20_update_clocks_update_dentist Acked-by:
Ian Chen <ian.chen@amd.com> Tested-by:
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Samson Tam authored
[Why & how] Fix format and typo of comments. Acked-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Oliver Logush authored
[Why and How] dwbc_funcs.set/get_privacy_mask isn't being used anymore, drop it Reviewed-by:
Oliver Logush <oliver.logush@amd.com> Tested-by:
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Aric Cyr authored
This version brings along the following: - DP fixes - Exiting idle optimizations on mouse updates Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Qingqing Zhuo authored
[Why] DIO parameters were missing in topology_update_intput_v3 struct. [How] Add DIO parameters in v3 struct and update in functions perspectively. Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Have option to exit idle opt on cursor updates for debug and optimizations purposes Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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hersen wu authored
[Why] when 4k@144hz dp connect to dp1.4 dsc mst hub, requested bandwidth exceeds caps of dsc hub. but dsc bw valid functions, increase_dsc_bpp, try_disable_dsc, pre_validate_dsc, compute_mst_dsc_configs_for_state, do not return false to atomic check. this cause user mode initiate mode set to kernel, then cause kernel assert, system hang. [How] dsc bandwidth valid functions return pass or fail to atomic check. Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
hersen wu <hersenxs.wu@amd.com> Tested-by:
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Shah Dharati authored
[Why & How] For a some specific monitors, when connected on boot or hot plug, monitor flash for 1/2 seconds can happen during first HDCP query operation. Ading some delay in the init sequence for these monitors fixes the issue, so it is implemented as monitor specific patch. Co-authored-by:
Shah Dharati <dharshah@amd.com> Reviewed-by:
Hansen Dsouza <Hansen.Dsouza@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] According to DP specs, in EQ DONE phase of link training, we should lower lane count when at least one CR DONE bit is set to 1, while lower link rate when all CR DONE bits are 0s. However in our code, we will treat both cases as latter. This is not exactly correct based on the specs expectation. [how] Check lane0 CR DONE bit when it is still set but CR DONE fails, we treat it as a partial CR DONE failure in EQ DONE phase, we will follow the same fallback flow as when ED DONE fails in EQ DONE phase. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Daniel Phillips authored
Add a new KFD ioctl to return the largest possible memory size that can be allocated as a buffer object using kfd_ioctl_alloc_memory_of_gpu. It attempts to use exactly the same accept/reject criteria as that function so that allocating a new buffer object of the size returned by this new ioctl is guaranteed to succeed, barring races with other allocating tasks. This IOCTL will be used by libhsakmt: https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg75743.htmlSigned-off-by:
Daniel Phillips <Daniel.Phillips@amd.com> Signed-off-by:
David Yat Sin <David.YatSin@amd.com> Reviewed-by:
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Chengming Gui authored
This reverts commit 2cfe34e1. Enable AGP aperture cause SDMA page fault for gfx11.0.2, so temp disable AGP aperture until SDMA FW resolved this. Reviewed-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
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Evan Quan authored
Enable BAMACO reset support for SMU 13.0.0. Signed-off-by:
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Evan Quan authored
The feature is ready with latest PMFW and IFWI. Signed-off-by:
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