- 29 Nov, 2023 31 commits
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Dennis Chan authored
[why] If Panel max link off frame count is low, it will cause low residency for Replay, then Disabled timing sync check in Full screen Video Case. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Dennis Chan <dennis.chan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Wayne Lin authored
[Why] MST relevant variables are maintained at drm side. As the result, we still have to call drm_dp_remove_payload_part2() to update the relevant values regardless the link is under mst mode or not. We used to have a workaround patch to tackle this: commit 3d8fcc67 ("drm/amd/display: Extract temp drm mst deallocation wa into its own function") Now it's time to remove the workaround and adjust the flow. [How] During deallocate_mst_payload(), source actually doesn't send out ALLOCATE_PAYLOAD at the end as like the flow in allocate_mst_payload(). Call function dm_helpers_dp_mst_send_payload_allocation() at the end of deallocate_mst_payload() is a bit confusing. Separate dm_helpers_dp_mst_send_payload_allocation() into 2 functions. Have a new function dm_helpers_dp_mst_update_mst_mgr_for_deallocation() to replace dm_helpers_dp_mst_send_payload_allocation() for payload deallocation. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
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Camille Cho authored
[Why] Remove the brightness cache in DC. It uses a single value to represent the brightness for both SDR and HDR mode. This leads to flash in HDR on/off. It also unconditionally programs brightness as in HDR mode. This may introduce garbage on SDR mode in miniLED panel. [How] Simplify the initialization flow by removing the DC cache and taking what panel has as default. Expand the mechanism for PWM to DPCD Aux to restore cached brightness value generally. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by:
Camille Cho <camille.cho@amd.com> Signed-off-by:
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Max Tseng authored
[Why] Sending certain Frameupdate number for Replay Power Evaluation Reviewed-by:
Max Tseng <max.tseng@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] If during driver init stage there are greater than 20 intermediary voltage states while constructing the SOC BB we could hit issues because we will index outside of the clock_limits array and start overwriting data. Increase the total number of states to 40 to avoid this issue. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
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Michael Strauss authored
[WHY] Currently DCN35 does not spread DPREFCLK [HOW] Remove hardcoded table with nonzero caps Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
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Max Tseng authored
Augment the function to allow send different format data in different use case. Reviewed-by:
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Bhuvana Chandra Pinninti authored
[why] To refactor DSC and make DSC files unit testable. [how] moved the dcnxx_dsc.c and .h files into corresponding dcn folders inside the dsc and cleared the linkage errors. Reviewed-by:
Bhuvana Chandra Pinninti <bhuvanachandra.pinninti@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] When choosing which dummy p-state latency to use, we need to use the DRAM speed from validation. The DRAMSpeed DML variable can change because we use different input params to DML when populating watermarks set B. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
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Ilya Bakoulin authored
[Why] Wrong function is used to translate LUT values to HW format, leading to visible artifacting in some cases. [How] Use the correct cm3_helper function. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We've updated the table but the values aren't being reflected in DML2 calculation. [How] Pass them into the bbox overrides. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
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Alex Sierra authored
Setting register to force ordering to prevent read/write or write/read hazards for un-cached modes. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Hawking Zhang authored
In nbio v7_9, host driver should not issu gpu reset Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Stanley Yang <Stanley.Yang@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We can override SR watermarks but not Z8 ones. [How] Add new parameters for Z8 matching the SR ones and feed them into the states. These also weren't being applied to every state, so make sure that we loop over and update all SOC states if given an override. Reviewed-by:
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Wenjing Liu authored
[why] In the new pipe resource management logic, the special handling for stereo timings is missing. This commit implements the same stereo timings handling as old pipe resource management code. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
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Wenjing Liu authored
[why] When ODM slice count is changed, otg master pipe's pixel clock params is no longer valid as the value is dependent on ODM slice count. Reviewed-by:
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Perry Yuan authored
The smu needs to get the rlc power down message to sync the rlc state with smu, the rlc state updating message need to be sent at while smu begin suspend sequence , otherwise SMU will crash while RLC state is not notified by driver, and rlc state probally changed after that notification, so it needs to notify rlc state to smu at the end of the suspend sequence in amdgpu_device_suspend() that can make sure the rlc state is correctly set to SMU. [ 101.000590] amdgpu 0000:03:00.0: amdgpu: SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x0000001E SMN_C2PMSG_82:0x00000000 [ 101.000598] amdgpu 0000:03:00.0: amdgpu: Failed to disable gfxoff! [ 110.838026] amdgpu 0000:03:00.0: amdgpu: SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x0000001E SMN_C2PMSG_82:0x00000000 [ 110.838035] amdgpu 0000:03:00.0: amdgpu: Failed to disable smu features. [ 110.838039] amdgpu 0000:03:00.0: amdgpu: Fail to disable dpm features! [ 110.838040] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]] *ERROR* suspend of IP block <smu> failed -62 [ 110.884394] PM: suspend of devices aborted after 21213.620 msecs [ 110.884402] PM: start suspend of devices aborted after 21213.882 msecs [ 110.884405] PM: Some devices failed to suspend, or early wake event detected Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
Perry Yuan <perry.yuan@amd.com> Signed-off-by:
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Hawking Zhang authored
Not needed anymore. Signed-off-by:
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Wenjing Liu authored
[why] In dcn32 DML pipes are ordered the same as dc pipes but only for used pipes. For example, if dc pipe 1 and 2 are used, their dml pipe indices would be 0 and 1 respectively. However update_pipe_slice_table_with_split_flags doesn't skip indices for free pipes. This causes us to not reference correct dml pipe output when building pipe topology. [how] Use two variables to iterate dc and dml pipes respectively and only increment dml pipe index when current dc pipe is not free. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
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Ian Chen authored
If the link requests to skip implicit eDP power control, we should honor that request. Reviewed-by:
Ian Chen <ian.chen@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why & How] Update to the new values per HW team request. Affects both stutter and z8. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
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Jonathan Kim authored
GC IP 9.4.2 and up support TA reporting of the number of xGMI links between peers. Tested-by:
Vignesh Chander <vignesh.chander@amd.com> Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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David Yat Sin authored
Fixes issue where user events of type KFD_EVENT_TYPE_HW_EXCEPTION do not have valid data Signed-off-by:
David Yat Sin <David.YatSin@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] DML2 means that the dcn3x policy for calculating z-state support no longer runs from validate_bandwidth. This means we are unconditionally allowing Z8, the hardware default. [How] Port the policy over to DCN35, but with a few modifications: - Don't use min_dst_y_next_start as a check for Z8/Z10 allow - Add support for overriding the Z10 stutter period per ASIC - Cleanup the code to make the policy assignment more clear Reviewed-by:
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Alvin Lee authored
When waiting for the ACK for INBOX0 message, we have to ensure to include the udelay for proper wait time Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
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Dennis Chan authored
[why] To support dynamic switching for Replay timing sync mechanism. Reviewed-by:
ChunTao Tso <chuntao.tso@amd.com> Acked-by:
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Lijo Lazar authored
Add sysfs attribute to read power management metrics. A snapshot is captured to the buffer when the attribute is read. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Lijo Lazar authored
Add support to fetch PM metrics sample from SMU v13.0.6 Signed-off-by:
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Lijo Lazar authored
Add API support to fetch a snapshot of power management metrics from PMFW. Signed-off-by:
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Srinivasan Shanmugam authored
Declaration of 'struct drm_device *dev' is redundant, as 'connector->dev' & 'dev_get_drvdata(kdev)' can be directly passed to 'drm_to_adev', without any intermediate DRM device 'dev' variable Cc: Roman Li <roman.li@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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André Almeida authored
Document what each amdgpu driver reset method does. Signed-off-by:
André Almeida <andrealmeid@igalia.com> Signed-off-by:
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- 17 Nov, 2023 9 commits
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Srinivasan Shanmugam authored
Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1373: warning: Function parameter or member 'xcc_mask' not described in 'amdgpu_vm_flush_compute_tlb' Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Prike Liang authored
Add trace for amdgpu runpm separate funcs usage and this will help debugging on the case of runpm usage missed to dereference. In the normal case the runpm usage count referred by one kind of functionality pairwise and usage should be changed from 1 to 0, otherwise there will be an issue in the amdgpu runpm usage dereference. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Acked-by:
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Alex Deucher authored
Define the pm metrics structures to be exposed via sysfs. Signed-off-by:
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Shiwu Zhang authored
By catting the xgmi_port_num sysfs node, it prints out the info in the format of <src node id>:<src port num> -> <dst node id>:<dst port num> for one xgmi link. For example, in case of 4 sockets fully and evenly connected setup, it would be like as below for the first node in the hive. 01:02 -> 02:03 01:03 -> 02:02 01:07 -> 03:04 01:04 -> 03:07 01:06 -> 04:05 01:05 -> 04:06 Based on the fact that there is two xgmi links between each socket pair, "01:02 -> 02:03" means that the current socket in question use the port 2 to connect with port 3 of the second node in the hive and so on. v2: print out the src/dst node id for each xgmi link (lijo) v3: replace the current_node++ with +1 to align with dst node (le) and use the dev_err instead of pr_err (lijo) v4: fix checkpatch warning (alex) Signed-off-by:Shiwu Zhang <shiwu.zhang@amd.com> Acked-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Aric Cyr authored
- Add missing chips for HDCP - Add new command to disable replay timing resync - Fix encoder disable logic - Enable DSC Flag in MST Mode Validation - Change the DMCUB mailbox memory location from FB to inbox - Add disable timeout option - Negate IPS allow and commit bits - Enable DCN clock gating for DCN35 - Prefer currently used OTG master when acquiring free pipe - Try to acquire a free OTG master not used in cur ctx first - Clear dpcd_sink_ext_caps if not set - Enable fast plane updates on DCN3.2 and above - Add null checks for 8K60 lightup - Refactor resource into component directory - Fix DSC not Enabled on Direct MST Sink - Guard against invalid RPTR/WPTR being set - Enable CM low mem power optimization - Fix a debugfs null pointer error Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Mario Limonciello authored
The PCIe speed capabilities advertised by a USB4 or TBT3 link are limited to PCIe gen 1 per the USB4 spec. In reality the speed will change dynamically based on fabric conditions and other traffic. DPM is disabled when dGPUs are connected directly to Intel hosts since the PCIe root port isn't able to handle dynamic speed switching. As this limitation is specifically for PCIe root ports in the SoC, don't apply it when connected to an eGPU enclosure connected to an Intel host. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2885Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Mario Limonciello authored
When bandwidth limits are looked up using pcie_bandwidth_available() virtual links such as USB4 are analyzed which might not represent the real speed. Furthermore devices may change speeds autonomously which may introduce conditional variation to the results reported in the status registers. Instead look at the capabilities of first PCI device outside of dGPU to decide upper limits that the dGPU will work at. For eGPU this effectively means that it will use the speed of the link partner. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2925#note_2145860 Link: https://www.usb.org/document-library/usb4r-specification-v20 USB4 V2 with Errata and ECN through June 2023 Section 11.2.1 Reviewed-by:
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Rodrigo Siqueira authored
[WHAT] Add missing HDCP ID in the message id enum. Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Anthony Koo authored
[WHY & HOW] Add new command to disable replay timing resync Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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