- 07 Apr, 2023 16 commits
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Douglas Anderson authored
Similar to sc7180 (see the patch ("arm64: dts: qcom: sc7180: Fix trogdor qspi pin config")), we should adjust the qspi pin config for sc7280. I won't re-describe all the research/arguments in the sc7180 patch here, but there are a few differences for sc7280 worth noting: 1. On herobrine the SPI flash (qspi) is wired up differently on the board. Rather than Cr50 and the AP being wired directly together, there's actually a mux that will _either_ connect the AP to the flash or Cr50 to the flash. This means that the internal pulls on Cr50 don't affect us and we should enable our own pulldowns. 2. On herobrine, EEs added an external pulldown on the MISO line. The argument in the schematic said that we added it (but not one on MOSI and CLK) because Cr50 already enabled pulldowns on MOSI and CLK. ...though, as per #1, those Cr50 pulldowns would only affect the line when the mux was swung to Cr50. The ironic result of #1 and #2 is that the external pulldowns on CLK/MISO/MOSI on herobrine are _exactly opposite_ of the ones on trogdor. 3. While I still don't have the actual exact schematics for all variants of IDP/CRD that were produced, I have some reference schematics that give me a belief of how the qspi is hooked up there. From this, I'm fairly certain that all of the older variants of IDP/CRD either have a pulldown on the CLK/MOSI/MISO lines (maybe through a direct connect to Cr50) or have no pull (in other words, they don't have a pullup). I'll go ahead and enable internal pulldowns on all the lines since that won't hurt to double-pull if there's an external pulldown and it's nice to have a pulldown if there's nothing external. Note that this only affects _older_ CRDs. Newer revs are considered "herobrine" (see the hoglin/zoglin device trees). 4. I didn't find the same strange "auto-switch-to-keeper" at suspend when probing on sc7280. Whatever pulls (or lack thereof) I left at suspend time seemed to persist into suspend. Signed-off-by:Douglas Anderson <dianders@chromium.org> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230323102605.13.Ib44c3e417c414a4227db8def75ded37ad368212c@changeid
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Douglas Anderson authored
In commit 7ec3e673 ("arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt") we specified the pull settings on the boot SPI (the qspi) data lines as pullups to "park" the lines. This seemed like the right thing to do, but I never really probed the lines to confirm. Since that time, I've done A LOT of research, experiements and poking of the lines with a voltmeter. A first batch of discoveries: - There is an external pullup on CS (clearly shown on schematics) - There are weak external pulldowns on CLK/MOSI (believed to be Cr50's internal pulldowns) - There is no pull on MISO. - When qspi isn't actively transferring it still drives CS, CLK, and MOSI. CS and MOSI are driven high and CLK is driven low. It does not drive MISO and (if no internal pulls are enabled) the line floats. The above means that it's good to have some sort of pull on MISO, at the very least. The pullup that we had before was actually fine (and my voltmeter confirms that it actually affected the state of the pin) but a pulldown would work equally well (and would match MOSI and CLK better). The above also means that we could save a tiny bit of power (not measurable by my setup) by setting up a sleep state for these pins. If nothing else this prevents us from driving high against Cr50's internal pulldown on MOSI. However, Qualcomm has also asserted in the past that it burns a little extra power to drive a pin, especially since these are configured with a slightly higher drive strength Let's fix all this. Since the external pulls are different for the two data lines, we'll split them into separate configs. Then we'll change the MISO pin to a pulldown and add a sleep state. On a slightly tangental (but not totally unrelated note), I also discovered some interesting things with these pins in suspend. First, I found that if we don't switch the pins to GPIO that the qspi peripheral continues to drive them in suspend. That'll be solved by what we're already doing above. Second, I found that something in the system suspend path (after Linux stops running) reconfigures these pins so that they don't have their normal pulls enabled but instead change to "keepers" (bias-bus-hold in DT speak). If a pin was floating before we entered suspend then it would stop floating. I found that I could manually pull a pin to a different level and then probe it and it would stay there. This is exactly keeper behavior. With the solution we have the switch to "keeper" doesn't matter too much but it's good to document. While talking about "keepers", it can also be noted that I found that the "keepers" on these pins were at least enough to win a fight against Cr50's internal pulls. That means it's best to make sure that the state of the pins are already correct before the mysterious transition to a keeper. Otherwise we'll burn (a small amount of) power in S3 via this fight. Luckily with the current solution we don't hit this case. NOTE: I've left "sc7180-idp" behavior totally alone in this patch. I didn't add a sleep state and I didn't change any pulls--I just adapted it to the fact that the data lines have separate configs. Qualcomm doesn't provide me with schematics for IDP and thus I don't actually know how the pulls are configured. Since this is just a development platform and worked well enough, it seems safer to leave it alone. Dependencies: - This patch has a hard dependency on ("pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLE"). Something in the boot code seemed to have been confused and thought it needed to set the "OUTPUT ENABLE" bit for these pins even though it was using them as SPI. Thus if we don't honor the "output-disable" property we could end up driving the SPI pins while in sleep mode. - In general, it's probably best not to backport this to a kernel that doesn't have commit d21f4b7f ("pinctrl: qcom: Avoid glitching lines when we first mux to output"). That landed a while ago, but it's still good to be explicit in case someone was backporting. If we don't have that then there might be a glitch when we first switch over to GPIO before we disable the output. - This patch _doesn't_ really have any dependency on the qspi driver patch that supports setting the pinctrl sleep state--they can go in either order. If we define the sleep state and the driver never selects it that's fine. If the driver tries to select a sleep state that we don't define that's fine. Signed-off-by:
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Douglas Anderson authored
As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable"), using "input-enable" in pinctrl states for Qualcomm TLMM pinctrl devices was either superfluous or there to disable a pin's output. Looking at cheza * ec_ap_int_l, h1_ap_int_odl: Superfluous. The pins will be configured as inputs automatically by the Linux GPIO subsystem (presumably the reference for other OSes using these device trees). * bios_flash_wp_l: Superfluous. This pin is exposed to userspace through the kernel's GPIO API and will be configured automatically. That means that in none of the cases for cheza did we need to change "input-enable" to "output-disable" and we can just remove these superfluous properties. Signed-off-by: -
Douglas Anderson authored
As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable"), using "input-enable" in pinctrl states for Qualcomm TLMM pinctrl devices was either superfluous or there to disable a pin's output. Looking at the sc7280-idp-ec-h1.dtsi file: * ap_ec_int_l, h1_ap_int_odl: Superfluous. The pins will be configured as inputs automatically by the Linux GPIO subsystem (presumably the reference for other OSes using these device trees). That means that in none of the cases for sc7280-idp-ec-h1.dtsi did we need to change "input-enable" to "output-disable" and we can just remove these superfluous properties. Signed-off-by: -
Douglas Anderson authored
As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable"), using "input-enable" in pinctrl states for Qualcomm TLMM pinctrl devices was either superfluous or there to disable a pin's output. Looking at trogdor: * ap_ec_int_l, fp_to_ap_irq_l, h1_ap_int_odl, p_sensor_int_l: Superfluous. The pins will be configured as inputs automatically by the Linux GPIO subsystem (presumably the reference for other OSes using these device trees). * bios_flash_wp_l: Superfluous. This pin is exposed to userspace through the kernel's GPIO API and will be configured automatically. That means that in none of the cases for trogdor did we need to change "input-enable" to "output-disable" and we can just remove these superfluous properties. Signed-off-by: -
Douglas Anderson authored
The l13a rail on trogdor devices has always been intended to be always-on on both S0 and S3. Different trogdor variants use l13a in slightly different ways, but the overall theme is that it's a 1.8V rail that the board uses for things that it wants powered in on S0 and S3. On many boards this includes the boot SPI (AKA qspi). For all intents and purposes this patch is actually a no-op since something else in the system seems to already be keeping the rail on all the time (confirmed via multimeter). That "something else" was postulated to be the modem but the rail is on / stays on even without the modem/wifi coming up so it's likely the boot config. In any case, making the fact that this is always-on explicit seems like a good idea. Signed-off-by:
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Douglas Anderson authored
There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: e1ce8539 ("arm64: dts: qcom: sdm845: Add qspi (quad SPI) node") Signed-off-by:
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Douglas Anderson authored
There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: 7720ea00 ("arm64: dts: qcom: sc7280: Add QSPI node") Signed-off-by:
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Douglas Anderson authored
There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: ba3fc649 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1") Signed-off-by:
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Bjorn Andersson authored
Merge branch 'ib-qcom-quad-spi' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into arm64-for-6.4 Merge the support for output-enable/disable in the pinctrl-msm driver, to ensure that bisection across the following SC7180/SC7280 DeviceTree changes result in something electrically sound. Signed-off-by:
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Devi Priya authored
Add initial device tree support for Qualcomm IPQ9574 SoC and AL02 board Co-developed-by:
Anusha Rao <quic_anusha@quicinc.com> Signed-off-by:
Poovendhan Selvaraj <quic_poovendh@quicinc.com> Signed-off-by:
Devi Priya <quic_devipriy@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Merge the IPQ9574 Global Clock Controller Devicetree binding, to make available the clock definitions used in the Devicetree source.
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Devi Priya authored
Add clock and reset ID definitions for ipq9574 Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Co-developed-by:
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Petr Vorel authored
This fixes memory overlap error: [ 0.000000] reserved@6300000 (0x0000000006300000--0x0000000007000000) overlaps with smem_region@6a00000 (0x0000000006a00000--0x0000000006c00000) smem_region is the same as in downstream (qcom,smem) [1], therefore split reserved memory into two sections on either side of smem_region. Not adding labels as it's not expected to be used. [1] https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-angler-3.10-marshmallow-mr1/arch/arm/boot/dts/qcom/msm8994.dtsi#948 Fixes: 380cd3a3 ("arm64: dts: msm8994-angler: fix the memory map") Signed-off-by:
Petr Vorel <pvorel@suse.cz> Signed-off-by:
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Petr Vorel authored
Angler's cont_splash_mem mapping is shorter in downstream [1], therefore 380cd3a3 was wrong. Obviously also 0e5ded92 was wrong (workaround which fixed booting at the time). This fixes error: [ 0.000000] memory@3401000 (0x0000000003401000--0x0000000005601000) overlaps with tzapp@4800000 (0x0000000004800000--0x0000000006100000) [1] https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-angler-3.10-marshmallow-mr1/arch/arm64/boot/dts/huawei/huawei_msm8994_angler_row_vn1/huawei-fingerprint.dtsi#16 Fixes: 380cd3a3 ("arm64: dts: msm8994-angler: fix the memory map") Fixes: 0e5ded92 ("arm64: dts: qcom: msm8994-angler: Disable cont_splash_mem") Signed-off-by:
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Douglas Anderson authored
Developers on the ChromeOS team generally want to be notified to review changes that affect Chromebook device tree files. While we could individually add developers, the set of developers and the time each one has available to review patches will change over time. Let's try adding a group list as a reviewer and see if that's an effective way to manage things. A few notes: * Though this email address is actually backed by a mailing list, I'm adding it as "R"eviewer and not "L"ist since it's not a publicly readable mailing list and it's intended just to have a few people on it. This also hopefully conveys a little more responisbility for the people that are part of this group. * I've added all sc7180 and sc7280 files here. At the moment I'm not aware of any non-Chromebooks being supported that use these chips. If later something shows up then we can try to narrow down. * I've added "sdm845-cheza" to this list but not the rest of "sdm845". Cheza never shipped but some developers still find the old developer boards useful and thus it continues to get minimal maintenance. Most sdm845 device tree work, however, seems to be for non-Chromebooks. Cc: Stephen Boyd <swboyd@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Acked-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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- 06 Apr, 2023 8 commits
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Kathiravan T authored
Add the nodes for QUP peripheral, PRNG and WDOG. While at it, enable the I2C device for MI01.2 board. Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
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Krzysztof Kozlowski authored
Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on Qualcomm SM8550. The nodes are very similar to SM8450, except missing NPL clock which is not exposed on SM8550 and should not be touched. Signed-off-by:
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Manivannan Sadhasivam authored
Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map" properties for the PCIe nodes. First one passes the SMR mask to the iommu driver and the latter specifies the SID for each PCIe device. But with "iommus" property, the PCIe controller will be added to the iommu group along with the devices. This makes no sense because the controller will not initiate any DMA transaction on its own. And moreover, it is not strictly required to pass the SMR mask to the iommu driver. If the "iommus" property is not present, then the default mask of "0" would be used which should work for all PCIe devices. On the other side, if the SMR mask specified doesn't match the one expected by the hypervisor, then all the PCIe transactions will end up triggering "Unidentified Stream Fault" by the SMMU. So to get rid of these hassles and also prohibit PCIe controllers from adding to the iommu group, let's remove the "iommus" property from PCIe nodes. Reported-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.orgSigned-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
The parent controller for both interrupts is GIC, so no need for interrupts-extended. Signed-off-by:
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Krzysztof Kozlowski authored
The parent controller for the interrupt is GIC, so no need for interrupts-extended. Signed-off-by:
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Krzysztof Kozlowski authored
The parent controller for both interrupts is GIC, so no need for interrupts-extended. Signed-off-by:
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Krzysztof Kozlowski authored
Use labels, instead of comments, for Soundwire controllers. Naming them is useful, because they are specialized and have also naming in datasheet/programming guide. Signed-off-by:
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Krzysztof Kozlowski authored
Use labels, instead of comments, for Soundwire controllers. Naming them is useful, because they are specialized and have also naming in datasheet/programming guide. Signed-off-by:
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- 05 Apr, 2023 16 commits
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Konrad Dybcio authored
Use the non-deprecated, SoC-specific DSI compatible. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Steev Klimaszewski authored
The Lenovo Thinkpad X13s has a WCN6855 Bluetooth controller on uart2, add this. Signed-off-by:
Steev Klimaszewski <steev@kali.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Tested-by:
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Bjorn Andersson authored
Add the definition for uart2 for sc8280xp devices. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Brian Masney <bmasney@redhat.com> Reviewed-by:
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Manivannan Sadhasivam authored
The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by:
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Manivannan Sadhasivam authored
The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by:
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Manivannan Sadhasivam authored
The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by:
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Bartosz Golaszewski authored
Set line names for GPIO lines exposed by PMICs on sa8775p-ride. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by:
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Bartosz Golaszewski authored
Add GPIO controller nodes to PMICs that have the GPIO hooked up on sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
Add the thermal zones and associated alarm nodes for the PMICs that have them hooked up on sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
Add the RESIN input for sa8775p platforms' PMIC. Signed-off-by:
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Bartosz Golaszewski authored
Add the power key node under the PON node for PMIC #0 on sa8775p. Signed-off-by:
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Bartosz Golaszewski authored
Add the PON node to PMIC #0 for sa8775p platforms. Signed-off-by:
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Bartosz Golaszewski authored
Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced to the SoC via SPMI. Enable the PMICs for sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
Add the SPMI PMIC Arbiter node for SA8775p platforms. Signed-off-by:
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Bartosz Golaszewski authored
Add the Power Domain Controller node for SA8775p. Signed-off-by:
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Bartosz Golaszewski authored
Sort all children of the soc node by the first address in their reg property. This was mostly already the case but there were some nodes that didn't follow it so fix it now for consistency. Signed-off-by:
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