- 09 Dec, 2021 10 commits
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Hans de Goede authored
Add support for eDP panels with a built-in privacy screen using the new drm_privacy_screen class. Changes in v3: - Move drm_privacy_screen_get() call to intel_ddi_init_dp_connector() Changes in v2: - Call drm_connector_update_privacy_screen() from intel_enable_ddi_dp() / intel_ddi_update_pipe_dp() instead of adding a for_each_new_connector_in_state() loop to intel_atomic_commit_tail() - Move the probe-deferral check to the intel_modeset_probe_defer() helper Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211005202322.700909-11-hdegoede@redhat.com
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Hans de Goede authored
The upcoming privacy-screen support adds another check for deferring probe till some other drivers have bound first. Factor out the current vga_switcheroo_client_probe_defer() check into an intel_modeset_probe_defer() helper, so that further probe-deferral checks can be added there. Reviewed-by:
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Ville Syrjälä authored
Since we got rid of the "_get_" from intel_get_crtc_for_pipe() let's do the same for intel_get_first_crtc() for consistency. Signed-off-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
Move intel_crtc_for_plane() next to its only user. No one else should ever use this. Signed-off-by:
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Ville Syrjälä authored
These plane/pipe->crtc mapping arrays are rather pointless. Get rid of them and just iterate the lists instead. Signed-off-by:
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Jani Nikula authored
Get the dependencies for merging drm-privacy-screen support. Signed-off-by: -
Jani Nikula authored
Add display/intel_display_trace.[ch] for defining display tracepoints. The main goal is to reduce cross-includes between gem and display. It would be possible split up tracing even further, but that would lead to more boilerplate. We end up having to include intel_crtc.h in a few places because it was pulled in implicitly via intel_de.h -> i915_trace.h -> intel_crtc.h, and that's no longer the case. There should be no changes to tracepoints. v3: - Rebase v2: - Define TRACE_INCLUDE_PATH relative to define_trace.h (Chris) - Remove useless comments (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/7862ad764fbd0748d903c76bc632d3d277874e5b.1638961423.git.jani.nikula@intel.com
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Jani Nikula authored
Follow the style that seems to be prevalent in kernel for undef and define of TRACE_SYSTEM, TRACE_INCLUDE_PATH, and TRACE_INCLUDE_FILE. There should be no changes to tracepoints. v2: Keep TRACE_INCLUDE_PATH relative to define_trace.h (Chris) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDaniel Vetter authored
drm-misc-next for 5.17: UAPI Changes: Cross-subsystem Changes: * Move 'nomodeset' kernel boot option into DRM subsystem Core Changes: * Replace several DRM_*() logging macros with drm_*() equivalents * panel: Add quirk for Lenovo Yoga Book X91F/L * ttm: Documentation fixes Driver Changes: * Cleanup nomodeset handling in drivers * Fixes * bridge/anx7625: Fix reading EDID; Fix error code * bridge/megachips: Probe both bridges before registering * vboxvideo: Fix ERR_PTR usage Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/YaSVz15Q7dAlEevU@linux-uq9g.fritz.box
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Madhumitha Tolakanahalli Pradeep authored
Changes since v2.12: - Release notes for v2.13: 1. Fix for simple flip queue with DC6v - Release notes for v2.14: 1. Fix for flip queue roll over cases with DC6v 2. Enhancement for residency 3. Workaround for 3Dlut restore issue v2: Commit message update (Imre) Signed-off-by:Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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- 08 Dec, 2021 4 commits
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Siva Mullati authored
Only hw that supports mappable aperture would hit this path vm_fault_gtt/vm_fault_tmm, So we never hit this function remap_io_mapping() in discrete, So skip this code for non-x86 architectures. v2: use IS_ENABLED () instead of #if defined v3: move function prototypes from i915_drv.h to i915_mm.h v4: added kernel error message in stub function v5: fixed compilation warnings v6: checkpatch style Signed-off-by:
Siva Mullati <siva.mullati@intel.com> Reviewed-by:
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Anusha Srivatsa authored
Though, RPL-S is defined as subplatform of ADL-S, unlike ADL-S, it has GuC submission by default. v2: Remove extra parenthesis (Jani) v3: s/IS_RAPTORLAKE/IS_ADLS_RPLS (Jani) Cc: dri-devel@lists.freedesktop.org Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Acked-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
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Anusha Srivatsa authored
Add the PCH ID for RPL-S. v2: Self contained commit message (Jani) Cc: dri-devel@lists.freedesktop.org Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Anusha Srivatsa authored
Raptor Lake S(RPL-S) is a version 12 Display, Media and Render. For all i915 purposes it is the same as Alder Lake S (ADL-S). Introduce RPL-S as a subplatform of ADL-S. This patch adds PCI ids for RPL-S. BSpec: 53655 Cc: x86@kernel.org Cc: dri-devel@lists.freedesktop.org Cc: Ingo Molnar <mingo@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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- 07 Dec, 2021 11 commits
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Ville Syrjälä authored
Supposedly we should be able to change the cdclk squasher waveform even when many pipes are active. Make it so. Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211119131348.725220-6-mika.kahola@intel.com
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Mika Kahola authored
To calculate CD clock with squasher unit, we set CD clock ratio to fixed value of 34. The CD clock value is read from CD clock squasher table. BSpec: 54034 v2: Read ratio from register (Ville) Drop unnecessary local variable (Ville) Get CD clock from the given table v3: Calculate CD clock frequency based on waveform bit pattern (Ville) [v4: vsyrjala: Actually do a proper blind readout from the hardware] [v5: vsyrjala: Use has_cdclk_squasher()] Signed-off-by: -
Mika Kahola authored
Set CD clock squashing registers based on selected CD clock. v2: use slk_cdclk_decimal() to compute decimal values instead of a specific table (Ville) Set waveform based on CD clock table (Ville) Drop unnecessary local variable (Ville) v3: Correct function naming (Ville) Correct if-else structure (Ville) [v4: vsyrjala: Fix spaces vs. tabs] [v5: vsyrjala: Fix cd2x divider calculation (Uma), Add warn to waveform lookup (Uma), Handle bypass freq in waveform lookup, Generalize waveform handling in bxt_set_cdclk()] Signed-off-by: -
Mika Kahola authored
In case of CD clock squashing the divider is always 1. We don't need to calculate the divider in use so let's skip that for DG2. v2: Drop unnecessary local variable (Ville) v3: Avoid if-else structure (Ville) [v4: vsyrjala: Fix cd2x divider calculation (Uma), Introduce has_cdclk_squasher()] Signed-off-by: -
Mika Kahola authored
For CD clock squashing method, we need to define corresponding CD clock table for reference clocks, dividers and ratios for all CD clock options. BSpec: 54034 v2: Add CD squashing waveforms as part of CD clock table (Ville) v3: Waveform is 16 bits wide (Ville) [v4: vsyrjala: Nuke the non-squasher based table, Set .divider=2 for consistency, Pack intel_cdclk_vals a bit nicer] v5: Fix error in waveform value (Swati) v6 (Lucas): Rebase on upstream v7 (MattR): Drop 40.8, 81.6, and 122.4 MHz frequencies to reflect new bspec update. Signed-off-by: -
Jani Nikula authored
Localize HOBL and low vswing VBT lookups to a couple of small helpers, and get rid of a bunch of local variables. Signed-off-by:
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Jani Nikula authored
The mode set sequence for 128b/132b requires setting the div32 version of MPLLB clock. Bspec: 53880, 54128 Signed-off-by:
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Uma Shankar authored
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for extended range. It has 511 entries for gamma with additional 2 entries for extended range. v2: Updated lut size for 10bit gamma, added lut_tests (Ville) v3: Dropped the gamma lut tests fields (Ville) Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Reviewed-by:
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Uma Shankar authored
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation to incorparate the extended lut size for XE_LPD. v2: Added a helper for degamma lut size (Ville) Signed-off-by:
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Uma Shankar authored
Enable pipe color support for Display 13 platforms. Currently limit to just 10bit gamma and later extend it for logarithmic gamma, once the new UAPI is agreed by community and implemented by a userspace consumer. v2: Updated dev_priv to i915 (Ville) Signed-off-by:
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Madhumitha Tolakanahalli Pradeep authored
Increase the max size of DMC on ADL-P to account for support of new features in the current/upcoming DMC versions. Signed-off-by:
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- 04 Dec, 2021 1 commit
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Clint Taylor authored
Remove force probe protection from ADL_P platform. Did not obsevre warnings, errors, flickering or any visual defects while doing ordinary tasks like browsing and editing documents in a two monitor setup. For more info drm-tip idle run results : https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html? Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by:
Jon Bloomfield <jon.bloomfield@intel.com> Signed-off-by:
Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
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- 03 Dec, 2021 14 commits
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Tejas Upadhyay authored
From VBT, ddc pin info suggests the following mapping: VBT DRIVER DDI TC1->ddc_pin=3 should translate to PORT_TC1->0x9 DDI TC2->ddc_pin=4 should translate to PORT_TC2->0xa DDI TC3->ddc_pin=5 should translate to PORT_TC3->0xb DDI TC4->ddc_pin=6 should translate to PORT_TC4->0xc Adding pin map to facilitate this translation as we cannot use existing icl ddc pin map due to conflict with DDI C and DDI TC1 info. Bspec:20124 v2: - Changed Author to Tejas Upadhyay Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Acked-by:Imre Deak <imre.deak@intel.com> Signed-off-by:
Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by:
Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Signed-off-by:
Raviteja Goud Talla <ravitejax.goud.talla@intel.com> Signed-off-by:
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Ville Syrjälä authored
Replace the "sizes are 0 based" stuff with just straight up -1 where needed. Less confusing all around. Signed-off-by:
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Ville Syrjälä authored
Now that each plane tracks its own no_fbc_reason we can print that out in debugfs, and we can also show which plane is currently selected for FBC duty. Signed-off-by:
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Ville Syrjälä authored
FBC and double wide pipe are mutually exclusive. Disable FBC when we have to resort to double wide. Signed-off-by:
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Ville Syrjälä authored
Rename the 'params' to just fbc state. Signed-off-by:
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Ville Syrjälä authored
Currently we track the FBC plane as a pointer under intel_fbc and also as a i9xx_plane_id under intel_fbc_state. Just store the pointer once in the fbc state. Signed-off-by:
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Ville Syrjälä authored
fbc->state_cache has now become useless. We can simply update the reg params directly from the plane/crtc states during __intel_fbc_enable(). Signed-off-by:
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Ville Syrjälä authored
Currently a FIFO underrun just causes FBC to be deactivated, and later checks then prevent it from being reactivated. We can simpify our lives a bit by logically disabling FBC on FIFO underruns. This avoids the funny intermediate state where FBC is logically enabled but can't actually be activated. v2: intel_wait_for_vblank() is no more Signed-off-by:
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Ville Syrjälä authored
Don't really see a good reason why we can't just do the vgpu and modparam checks already in intel_fbc_check_plane(). Signed-off-by:
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Ville Syrjälä authored
In the future we may have more than one FBC instance on some platforms. So let's just allocate it dynamically. This also lets us fully hide the implementation from prying eyes. Signed-off-by:
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Ville Syrjälä authored
In order to better encapsulate the FBC implementation introduce a small helper to do the plane<->FBC instance association. We'll also try to structure the plane init code such that introducing multiple FBC instances will be easier down the line. Signed-off-by:
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Ville Syrjälä authored
In order to encapsulate FBC harder let's just move the debugfs stuff into intel_fbc.c. Signed-off-by:
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Ville Syrjälä authored
The underrun code doesn't need to know any details about FBC, so just pass in the whole device rather than a specific FBC instance. We could make this a bit more fine grained by also passing in the pipe to intel_fbc_handle_fifo_underrun_irq() and letting the FBC code figure which FBC instance (if any) is active on said pipe. But that seems a bit overkill for this so don't bother. Signed-off-by:
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Ville Syrjälä authored
Use an early return to flatten most of __intel_fbc_pre_update(). Signed-off-by:
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