- 13 Jul, 2022 21 commits
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Samson Tam authored
[Why] With single display odm 2:1 policy, when moving windowed MPO across the display, we experience a momentary lag when we move between the centre of the display and the right half of the display. This is caused by the MPO pipe being reallocated when it crosses this boundary [How] Handle two cases: 1. if the head pipe has a MPO pipe already allocated in the old context, then use that pipe if it is available in the current context 2. if the head pipe is on the left side, check the right side to see if it has a MPO pipe already allocated. If so, don't use that pipe if it is selected as the idle pipe in the current context Add new function pointer called .acquire_idle_pipe_for_head_pipe that will pass in the head pipe and handle case 1 Add find_idle_secondary_pipe_check_mpo() to handle case 2 if we don't hit case 1. In dc_add_plane_to_context(), start with head pipe and check case 1 and 2 in call acquire_free_pipe_for_head(). If we are on the right side of the display, check case 1 again by passing in right side pipe as the new head in call acquire_free_pipe_for_head(). Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Aurabindo Pillai authored
[Why&How] Add a field to store the NBIO IP offset for use with runtime offset calculation Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Harry Wentland authored
[Why&How] Add a field to store the DCN IP offset for use with runtime offset calculation This offset is indexed using reg*_BASE_IDX for the corresponding group of registers. For example, address of DIG_BE_CNTL instance 0 is calculated like: dcn_reg_offsets[regDIG0_DIG_BE_CNTL_BASE_IDX] + regDIG0_DIG_BE_CNTL. {dcn,nbio}_reg_offsets are used only for the ASICs for which runtime initializaion of offsets are enabled through the modified SR* macros that contain an additional REG_STRUCT element in the macro definition. DCN3.5+ will fail dc_create() if {dcn,nbio}_reg_offsets are null. They are applicable starting with DCN32/321 and are not used for ASICs upstreamed before them. ASICs before DCN32/321 will not contain any computation that involves {dcn,nbio}_reg_offsets. For them, the address/offset computation is done during compile time. This is evident from the BASE_INNER definition for compile time vs run time initialization: Compile time init: #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg Run time init: #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] BASE_INNER macro is local to each dcnxx_resource.c and hence different ASICs can have either runtime or compile time initialization of offsets. The computation of offset is done for registers all at once during driver load and hence it does not introduce any performance overhead during normal operation. Reviewed-by:Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Charlene Liu authored
[why] insert log for debug use. v2: squash in fix (Alex) Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Wayne Lin authored
[Why & How] There is chance we change dc state while calling dc_link_detect(). As the result of that, grab the dm.dc_lock before detecting link. Reviewed-by:
Hersen Wu <hersen.wu@amd.com> Acked-by:
Wayne Lin <Wayne.Lin@amd.com> Tested-by:
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Ethan Wellenreiter authored
[Why] ABGR16161616 colour format was added to dcn10/20/30, and set any ARGB16161616 to the same value as it (26). As such, the HDR10 Green Point y value was too far off of the EDID stated value for DisplayPort. [How] Added back the pixel format as 22 for ARGB16161616 for dcn10/20/30. Reviewed-by:
Reza Amini <reza.amini@amd.com> Acked-by:
Ethan Wellenreiter <Ethan.Wellenreiter@amd.com> Tested-by:
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Aric Cyr authored
Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Jun Lei authored
[why] Unbounded request logic in resource/DML has some issues where unbounded request is being enabled incorrectly. SW today enables unbounded request unconditionally in hardware, on the assumption that HW can always support it in single pipe scenarios. This worked until now because the same assumption is made in DML. A new DML update is needed to fix a bug, where there are single pipe scenarios where unbounded cannot be enabled, and this change in DML needs to be ported in, and dcn32 resource logic fixed. [how] First, dcn32_resource should program unbounded req in HW according to unbounded req enablement output from DML, as opposed to DML input Second, port in DML1 update which disables unbounded req in some scenarios to fix an issue with poor stutter performance Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Tested-by:
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Jack Xiao authored
Port aggregated doorbell support to gfx11. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jack Xiao authored
Port aggregated doorbell support to sdma6. Signed-off-by:
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Le Ma authored
Ring aggregated doorbel to make unmapped queue scheduled in mes firmware. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Jack Xiao authored
Allocate and enable aggregated doorbell. Signed-off-by:
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Le Ma authored
Allocate and enable aggregated doorbell. Signed-off-by:
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Likun Gao authored
Move reset_context out of gpu recover function to make it configurable for different reset purpose. For the reset way of call gpu_recovery sysfs, force to use full reset method. Otherwise, try soft reset by default if the related ASIC supportted, if soft reset failed, will use full reset. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Likun Gao authored
Support SDMA soft reset for SDMA v6. V3: use ib test to check soft reset. V4: squash in unused variable fix (Alex) Signed-off-by:
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Likun Gao authored
Enable soft reset for gfx 11. V2: enable both gfx v11.0.0 and gfx v11.0.2. Signed-off-by:
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Likun Gao authored
Support GFX soft reset for gfx v11. V3: use ib test check soft reset. V4: squash in unused variable fix (Alex) Signed-off-by:
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Chris Park authored
[Why] Status flags definition is reduced to read less bytes in SCDC transaction for status update. [How] Reduce definition of reserved bytes from 3 to 1 for status update. Reviewed-by:
Chris Park <chris.park@amd.com> Tested-by:
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Prike Liang authored
On the GC 10.3.7 platform the initial MEC release version #3 can support atomic operation,so need correct and set its MEC atomic support version to #3. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] Ideally link capability should be independent from the link configuration that we decide to use in enable link. Otherwise if link capability is changed after validation has completed, we could end up enabling a link configuration with invalid configuration. This would lead to over link bandwidth subscription or in the extreme case causes us to enable HPO link to a DIO stream. [how] Add a new struct in pipe ctx called link config. This structure will contain link configuration to enable a link. It will be populated during map pool resources after we validate link bandwidth. Remove the reference of verified link cap during enable link process and use link config in pipe ctx instead. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Fangzhi Zuo authored
[why] First MST sideband message returns AUX_RET_ERROR_HPD_DISCON on certain intel platform. Aux transaction considered failure if HPD unexpected pulled low. The actual aux transaction success in such case, hence do not return error. [how] Not returning error when AUX_RET_ERROR_HPD_DISCON detected on the first sideband message. v2: squash in additional DMI entries v3: squash in static fix Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Acked-by:
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- 12 Jul, 2022 14 commits
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Eric Huang authored
To expose unified memory for ctx save/resotre area feature availablity to libhsakmt. Proposed userspace: https://patchwork.freedesktop.org/series/106218/Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Samson Tam authored
[Why] When playing NV12 1080p MPO video, it is pipe splitting so we see two pipes in fullscreen and four pipes in windowed mode. Pipe split is happening because we are setting MaximumMPCCombine = 1 [How] Algorithm for MaximumMPCCombine has extra conditions we do not need. Use DCN31 algorithm instead Signed-off-by:
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Ilya Bakoulin authored
[Why] Black screen encountered when disabling Freesync through OSD on some displays. [How] Set the should_disable flag when new top pipe has no plane state to ensure that pipes get cleaned up. Reviewed-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by:
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Robin Chen authored
[Why] Some specific sink is not able to support PSRSU when DSC is turned on. For this case, fall-back to use PSR1. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Robin Chen <po-tchen@amd.com> Tested-by:
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Wayne Lin authored
[Why] When unplug one sst monitor from a mst hub and plug in the same port with another sst monitor, we don't read the corresponding edid. That's because we detect there is already an edid stored in aconnector->edid which is a stale one. [How] Clean up aconnector->edid when unplug mst connector. Reviewed-by:
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Samson Tam authored
[Why] In single display configuration, windowed MPO does not work with ODM combine. [How] For ODM + MPO window on one half of ODM, only 3 pipes should be allocated and scaling parameters adjusted to handle this case. Otherwise, we use 4 pipes. Move copy_surface_update_to_plane() before dc_add_plane_to_context() so that it gets the updated rect information when setting up the pipes. Add dc_check_boundary_crossing_for_windowed_mpo_with_odm() to force a full update when we cross a boundary requiring us to reconfigure the number of pipes between 3 and 4 pipes. Set config.enable_windowed_mpo_odm to true when we have the debug.enable_single_display_2to1_odm_policy set to true. Don't fail validating ODM with windowed MPO if config.enable_windowed_mpo_odm is true. Reviewed-by:
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Saaem Rizvi authored
[WHY] Assert statements causing several bugs on Linux DM [HOW] Removing assert statement for Linux DM (ASSERT(result == VBIOSSMC_Result_OK)). Also adding logging statements for setting dcfclk. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=216092 Fixes: c1b972a1 ("drm/amd/display: Insert pulling smu busy status before sending another request") Reviewed-by:
Gabe Teeger <Gabe.Teeger@amd.com> Acked-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by:
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Muhammad Ansari authored
[WHY] Needed a helper function for ALPM DPCD initialization [HOW] Refactoring to put ALPM initialization in a helper function Reviewed-by:
Muhammad Ansari <muansari@amd.com> Tested-by:
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Wesley Chalmers authored
[WHY] Certain DP 2.0 modes may fail validation if DP 2.0 is not considered for ODM combine. Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by:
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Alvin Lee authored
[Description] Exit SubVP if MPO is in use since SubVP + MPO together is not supported. - Don't add SubVP at validation time if we see MPO is in use Issues fixed in the SubVP / MPO transition: 1. Enable phantom pipes in post unlock function to prevent underflow when an active pipe is being transitioned to be a phantom pipe (VTG updates take place right away). Also must wait for VUPDATE of the main pipe to complete first 2. Don't wait for MPCC idle when transitioning a phantom pipe to an actual pipe. MPCC_STATUS is never asserted due to OTG being off for phantom pipes 3. When transitioning an active pipe to phantom, program DET right away (same as disabling the pipe) or the DET update will only take when the phantom pipe is enabled which can cause DET allocation errors. 4. For K1/K2 programming of phantom pipes, use same settings as the main pipe. Also don't program K1 / K2 = 0xF ever since the field is only 1 / 2 bits wide. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Jack Xiao authored
Set corresponding ready flag for mes ring when enable or disable mes ring. Signed-off-by:
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xinhui pan authored
That has been done in BO release notify. Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Alex Deucher authored
For GMC 10 parts which support scatter/gather display (display from system memory), we should allocate a larger gart size to better handler larger displays. This mirrors what we already do for GMC 9 parts. v2: fix typo (Alex) Acked-by:
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Jack Xiao authored
Need reserve buffers before unmap mes ctx bo va. v2: fix removal of dma_resv_excl_fence() (Alex) v3: fix dma_resv_usage (Alex) Signed-off-by:
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- 08 Jul, 2022 5 commits
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Jack Xiao authored
For some cases (accessing registers, unmap legacy queue), it needs access mes in atomic context. Use spinlock to protect agaist mes ring buffer race condition. Signed-off-by:
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Kenneth Feng authored
drop the thermal_controller_type check since it's not relevant. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Kenneth Feng authored
fixed the issue: gpu runs in dc mode but it is expected to be in ac mode. this causes the lower performance on smu_v13_0 Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Output Data Mapping is a power saving feature that allows us to run at reduced DPP and DISP clocks compared to what could be achieved with a single pipe. Set the default policy for single display use case to use 2 to 1 ODM combine. The options are queried by DC and appropriate register programming sequence is initiated to enable this feature. Fixes: 235c6763 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Add a missing callback to set DIG FIFO output pixel mode. This is used when ODM combine is activated. Fixes: 235c6763 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by:
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