- 15 Oct, 2021 32 commits
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Rob Clark authored
Add a short delay before clamping to idle frequency on active->idle transition. It takes ~0.5ms to increase the freq again on the next idle->active transition, so this helps avoid extra freq transitions on workloads that bounce between CPU and GPU. Signed-off-by:
Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20210927230455.1066297-2-robdclark@gmail.comSigned-off-by:
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Rob Clark authored
Before open-coding this a 2nd time, add a helper. Signed-off-by:
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Bjorn Andersson authored
Not all platforms has P0 at an offset of 0x1000 from the base address, so add support for specifying each sub-region in DT. The code falls back to the predefined offsets in the case that only a single reg is specified, in order to support existing DT. Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211001174400.981707-6-bjorn.andersson@linaro.orgSigned-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Bjorn Andersson authored
Not all platforms has DP_P0 at offset 0x1000 from the beginning of the DP block. So split the dss_io_data memory region into a set of sub-regions, to make it possible in the next patch to specify each of the sub-regions individually. Reviewed-by:
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Bjorn Andersson authored
In order to deal with multiple memory ranges in the following commit change the ioremap wrapper to not poke directly into the dss_io_data struct. While at it, devm_ioremap_resource() already prints useful error messages on failure, so omit the unnecessary prints from the caller. Signed-off-by:
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Bjorn Andersson authored
The non-devres version of ioremap is used, which requires manual cleanup. But the code paths leading here is mixed with other devres users, so rely on this for ioremap as well to simplify the code. Reviewed-by:
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Bjorn Andersson authored
reg was defined as one region covering the entire DP block, but the memory map is actually split in 4 regions and obviously the size of these regions differs between platforms. Switch the reg to require that all four regions are specified instead. It is expected that the implementation will handle existing DTBs, even though the schema defines the new layout. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Dan Carpenter authored
The msm_iommu_new() returns error pointers on failure so check for that to avoid an Oops. Fixes: ccac7ce3 ("drm/msm: Refactor address space initialization") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Dan Carpenter authored
There are two problems here: 1) The "seqptr" is used uninitalized when we free it at the end. 2) The a6xx_gmu_get_mmio() function returns error pointers. It never returns true. Fixes: 64245fc5 ("drm/msm/a6xx: use AOP-initialized PDC for a650") Fixes: f8fc924e ("drm/msm/a6xx: Fix PDC register overlap") Signed-off-by:
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Dmitry Baryshkov authored
The DSI host might be left in some state by the bootloader. If this state generates an IRQ, it might hang the system by holding the interrupt line before the driver sets up the DSI host to the known state. Move the request_irq into msm_dsi_host_init and pass IRQF_NO_AUTOEN to it. Call enable/disable_irq after msm_dsi_host_power_on/_off() functions, so that we can be sure that the interrupt is delivered when the host is in the known state. It is not possible to defer the interrupt enablement to a later point, because drm_panel_prepare might need to communicate with the panel over the DSI link and that requires working interrupt. Fixes: a689554b ("drm/msm: Initial add DSI connector support") Signed-off-by:
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Vladimir Lypak authored
MDP version v1.16 is almost identical to v1.15 with most significant difference being presence of second DSI interface. MDP v1.16 is found on SoCs such as MSM8x53, SDM450, SDM632 (All with Adreno 506). Signed-off-by:
Vladimir Lypak <vladimir.lypak@gmail.com> Signed-off-by:
Sireesh Kodali <sireeshkodali1@gmail.com> Reviewed-by:
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Vladimir Lypak authored
Add phy configuration for 14nm dsi phy found on MSM8953 SoC. Only difference from existing configurations are io_start addresses. Signed-off-by:
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Sireesh Kodali authored
SoCs based on the MSM8953 platform use the 14nm DSI PHY driver Signed-off-by:
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Wang Qing authored
dev_pm_opp_find_freq_exact never return null but ERR_PTR(),so we should use IS_ERR() to clarify and avoid compilation warnings. Signed-off-by:
Wang Qing <wangqing@vivo.com> Link: https://lore.kernel.org/r/1604630714-6163-1-git-send-email-wangqing@vivo.comSigned-off-by:
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Deepak R Varma authored
Using DEFINE_DEBUGFS_ATTRIBUTE macro with debugfs_create_file_unsafe() function in place of the debugfs_create_file() function will make the file operation struct "reset" aware of the file's lifetime. Additional details here: https://lists.archive.carbon60.com/linux/kernel/2369498 Issue reported by Coccinelle script: scripts/coccinelle/api/debugfs/debugfs_simple_attr.cocci Signed-off-by:
Deepak R Varma <mh12gx2825@gmail.com> Link: https://lore.kernel.org/r/9ca2c2e4cbd9ebb282b90f742305fd9b481aacc2.1603998014.git.mh12gx2825@gmail.comSigned-off-by:
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Bernard authored
Delete the conversion from bool value to bool function return. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Link: https://lore.kernel.org/r/AI*ANACSDfnjQejyeNXUnKoQ.1.1604995827401.Hmail.bernard@vivo.comSigned-off-by:
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Xu Wang authored
Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Signed-off-by:
Xu Wang <vulab@iscas.ac.cn> Reviewed-by:
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Xu Wang authored
Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Signed-off-by:
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Xu Wang authored
Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Signed-off-by:
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Bernard Zhao authored
Fix sparse warning: drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:1195:41: warning: Using plain integer as NULL pointer drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:1348:32: warning: Using plain integer as NULL pointer Signed-off-by:
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Tim Gardner authored
Coverity complains of a possible NULL dereference: CID 120718 (#1 of 1): Dereference null return value (NULL_RETURNS) 23. dereference: Dereferencing a pointer that might be NULL state->bos when calling msm_gpu_crashstate_get_bo. [show details] 301 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj, 302 submit->bos[i].iova, submit->bos[i].flags); Fix this by employing the same state->bos NULL check as is used in the next for loop. Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: linux-arm-msm@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org Signed-off-by:Tim Gardner <tim.gardner@canonical.com> Reviewed-by:
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Colin Ian King authored
The variable bpp is being initialized with a value that is never read, it is being updated later on in both paths of an if statement. The assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Reviewed-by:
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Rob Clark authored
These aren't used. And if we add use for them later, we should probably do something a bit more structured than string parsing. Signed-off-by:
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Rob Clark authored
For now, since we have a mix of bridges which support this flag, which which do *not* support this flag, or work both ways, try it once with NO_CONNECTOR and then fall back to the old way if that doesn't work. Eventually we can drop the fallback path. v2: Add missing drm_connector_attach_encoder() so display actually comes up when the bridge properly handles the NO_CONNECTOR flag Signed-off-by:Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
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Rikard Falkeborn authored
The only usage of hdmi_8996_pll_ops is to assign its address to the ops field in the clk_init_data struct, and the only usage of pll_init is to assign its address to the init field in the clk_hw struct, both which are pointers to const. Make them const to allow the compiler to put them in read-only memory. Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by:
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Marijn Suijten authored
div_u64_rem provides the result of the division and additionally the remainder; don't use this function to solely calculate the remainder while calculating the division again with div_u64. A similar improvement was applied earlier to the 10nm pll in 5c191fef ("drm/msm/dsi_pll_10nm: Fix dividing the same numbers twice"). Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-By:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by:
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zhaoxiao authored
Address the following checkpatch errors: ERROR: do not initialise statics to false FILE: :drivers/gpu/drm/msm/msm_drv.c:21: -static bool reglog = false; FILE: :drivers/gpu/drm/msm/msm_drv.c:31: -bool dumpstate = false; Signed-off-by:
zhaoxiao <long870912@gmail.com> Link: https://lore.kernel.org/r/20210906064315.4975-1-long870912@gmail.comSigned-off-by:
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Chi Minghao authored
Fix the following coccicheck REVIEW: ./drivers/gpu/drm/msm/edp/edp_ctrl.c:1245:5-8 Unneeded variable Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Chi Minghao <chi.minghao@zte.com.cn> Reviewed-by:
Lyude Paul <lyude@redhat.com> Reviewed-by:
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Mark Yacoub authored
[why] vsync_cnt atomic counter increments for every hw vsync. On the other hand, frame count is a register that increments when the frame gets actually pushed out. We cannnot read this register whenever the timing engine is off, but vblank counter should still return a valid number. This behavior also matches the downstream driver. [How] Read the encoder vsync count instead of the dpu_encoder_phys frame count. Suggested-by:
Mark Yacoub <markyacoub@chromium.org> Reviewed-by:
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Dmitry Baryshkov authored
As dpu_core_irq was merged into dpu_hw_intr, merge data structures too, removing the need for a separate data structure. Signed-off-by:
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Dmitry Baryshkov authored
We already clear the IRQ status register before processing IRQs, so do not clear the register again. Especially do not clear the IRQ status _after_ processing the IRQ as this way we can loose the event. Signed-off-by:
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Dmitry Baryshkov authored
With dpu_core_irq being the wrapper around dpu_hw_interrupts, there is little sense in having them separate. Squash them together to remove another layer of abstraction (hw_intr ops). Signed-off-by:
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- 12 Oct, 2021 8 commits
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Dan Carpenter authored
This disables a lock which wasn't enabled and it does not disable the first lock in the array. Fixes: 6e0eb52e ("drm/msm/dsi: Parse bus clocks from a list") Signed-off-by:
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Dan Carpenter authored
Return an error code if msm_dsi_manager_validate_current_config(). Don't return success. Fixes: 8b03ad30 ("drm/msm/dsi: Use one connector for dual DSI mode") Signed-off-by:
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Marijn Suijten authored
The downstream driver models this PLL lock check as an if-elseif-else. The only way to reach the else case where pll_locked=true [1] is by succeeding both readl_poll_timeout_atomic calls (which return zero on success) in the if _and_ elseif condition. Hence both the "lock" and "ready" bit need to be tested in the SM_READY_STATUS register before considering the PLL locked and ready to go. Tested on the Sony Xperia XA2 Ultra (nile-discovery, sdm630). [1]: https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/drivers/clk/qcom/mdss/mdss-dsi-pll-14nm-util.c?h=LA.UM.9.2.1.r1-08000-sdm660.0#n302 Fixes: f079f6d9 ("drm/msm/dsi: Add PHY/PLL for 8x96") Signed-off-by:
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Dmitry Baryshkov authored
The commit 9f91f22a ("drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances") mistakenly changed registered clock names. While the platform is in progress of migration to using clock properties in the dts rather than the global clock names, we should provide backwards compatibility. Thus restore registerd global clock names. Fixes: 9f91f22a ("drm/msm/dsi: remove duplicate fields from dsi_pll_Nnm instances") Signed-off-by:
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Robert Foss authored
Both PINGPONG4 and PINGPONG5 IRQ registers are using the same address, which is incorrect. PINGPONG4 should use the register offset 30, and PINGPONG5 should use the register offset 31 according to the downstream driver. Fixes: 667e9985 ("drm/msm/dpu: replace IRQ lookup with the data in hw catalog") Signed-off-by:
Robert Foss <robert.foss@linaro.org> Reviewed-by:
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Fabio Estevam authored
Since commit 98659487 ("drm/msm: add support to take dpu snapshot") the following NULL pointer dereference is seen on i.MX53: [ 3.275493] msm msm: bound 30000000.gpu (ops a3xx_ops) [ 3.287174] [drm] Initialized msm 1.8.0 20130625 for msm on minor 0 [ 3.293915] 8<--- cut here --- [ 3.297012] Unable to handle kernel NULL pointer dereference at virtual address 00000028 [ 3.305244] pgd = (ptrval) [ 3.307989] [00000028] *pgd=00000000 [ 3.311624] Internal error: Oops: 805 [#1] SMP ARM [ 3.316430] Modules linked in: [ 3.319503] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.14.0+g682d702b426b #1 [ 3.326652] Hardware name: Freescale i.MX53 (Device Tree Support) [ 3.332754] PC is at __mutex_init+0x14/0x54 [ 3.336969] LR is at msm_disp_snapshot_init+0x24/0xa0 i.MX53 does not use the DPU controller. Fix the problem by only calling msm_disp_snapshot_init() on platforms that use the DPU controller. Cc: stable@vger.kernel.org Fixes: 98659487 ("drm/msm: add support to take dpu snapshot") Signed-off-by:
Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210914174831.2044420-1-festevam@gmail.comSigned-off-by:
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Dan Carpenter authored
These error paths returned 1 on failure, instead of a negative error code. This would lead to an Oops in the caller. A second problem is that the check for "if (ret != -ENODATA)" did not work because "ret" was set to 1. Fixes: 5785dd7a ("drm/msm: Fix duplicate gpu node in icc summary") Signed-off-by:
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Dan Carpenter authored
This code returns 1 on error instead of a negative error. It leads to an Oops in the caller. A second problem is that the check for "if (ret != -ENODATA)" cannot be true because "ret" is set to 1. Fixes: 5785dd7a ("drm/msm: Fix duplicate gpu node in icc summary") Signed-off-by:
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