1. 21 Oct, 2011 3 commits
  2. 20 Oct, 2011 28 commits
  3. 12 Oct, 2011 2 commits
  4. 06 Oct, 2011 7 commits
    • Keith Packard's avatar
      drm/i915: Disable eDP VDD in a delayed work proc instead of synchronously · bd943159
      Keith Packard authored
      There's no good reason to turn off the eDP force VDD bit synchronously
      while probing devices; that just sticks a huge delay into all mode
      setting paths. Instead, queue a delayed work proc to disable the VDD
      force bit and then remember when that fires to ensure that the
      appropriate delay is respected before trying to turn it back on.
      Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
      bd943159
    • Keith Packard's avatar
      drm/i915: Create helper functions to determine eDP power state · ebf33b18
      Keith Packard authored
      We need to check eDP VDD force and panel on in several places, so
      create some simple helper functions to avoid duplicating code.
      Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
      ebf33b18
    • Keith Packard's avatar
      drm/i915: edp_panel_on does not need to return a bool · 7d639f35
      Keith Packard authored
      The return value was unused, so just stop doing that.
      Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
      Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      7d639f35
    • Keith Packard's avatar
      drm/i915: Move eDP panel fixed mode from dev_priv to intel_dp · d15456de
      Keith Packard authored
      This value doesn't come directly from the VBT, and so is rather
      specific to the particular DP output.
      Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
      Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      d15456de
    • Keith Packard's avatar
      drm/i915: Correct eDP panel power sequencing delay computations · f01eca2e
      Keith Packard authored
      Store the panel power sequencing delays in the dp private structure,
      rather than the global device structure. Who knows, maybe we'll get
      more than one eDP device in the future.
      
      From the eDP spec, we need the following numbers:
      
       T1 + T3	Power on to Aux Channel operation (panel_power_up_delay)
      
      		This marks how long it takes the panel to boot up and
      		get ready to receive aux channel communications.
      
       T8		Video signal to backlight on (backlight_on_delay)
      
      		Once a valid video signal is being sent to the device,
      		it can take a while before the panel is actuall
      		showing useful data. This delay allows the panel
      		to get something reasonable up before the backlight
      		is turned on.
      
       T9		Backlight off to video off (backlight_off_delay)
      
      		Turning the backlight off can take a moment, so
      		this delay makes sure there is still valid video
      		data on the screen.
      
       T10		Video off to power off (panel_power_down_delay)
      
      		Presumably this delay allows the panel to perform
      		an orderly shutdown of the display.
      
       T11 + T12	Power off to power on (panel_power_cycle_delay)
      
      		So, once you turn the panel off, you have to wait a
      		while before you can turn it back on. This delay is
      		usually the longest in the entire sequence.
      
      Neither the VBIOS source code nor the hardware documentation has a
      clear mapping between the delay values they provide and those required
      by the eDP spec. The VBIOS code actually uses two different labels for
      the delay values in the five words of the relevant VBT table.
      
      **** MORE LATER ***
      
      Look at both the current hardware register settings and the VBT
      specified panel power sequencing timings. Use the maximum of the two
      delays, to make sure things work reliably. If there is no VBT data,
      then those values will be initialized to zero, so we'll just use the
      values as programmed in the hardware. Note that the BIOS just fetches
      delays from the VBT table to place in the hardware registers, so we
      should get the same values from both places, except for rounding.
      
      VBT doesn't provide any values for T1 or T2, so we'll always just use
      the hardware value for that.
      
      The panel power up delay is thus T1 + T2 + T3, which should be
      sufficient in all cases.
      
      The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
      for T11, which isn't available anywhere.
      
      For the backlight delays, the eDP spec says T6 + T8 is the delay from the
      end of link training to backlight on and T9 is the delay from
      backlight off until video off. The hardware provides a 'backlight on'
      delay, which I'm taking to be T6 + T8 while the VBT provides something
      called 'T7', which I'm assuming is s
      
      On the macbook air I'm testing with, this yields a power-up delay of
      over 200ms and a power-down delay of over 600ms. It all works now, but
      we're frobbing these power controls several times during mode setting,
      making the whole process take an awfully long time.
      Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
      f01eca2e
    • Keith Packard's avatar
      drm/i915: Ensure eDP powered up during DP_SET_POWER operation in dp_prepare · f58ff854
      Keith Packard authored
      Any call to intel_dp_sink_dpms must ensure that the panel has power so
      that the DP_SET_POWER operation will be correctly received. The only
      one missing this was in intel_dp_prepare.
      Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
      Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      f58ff854
    • Keith Packard's avatar
      drm/i915: Enable eDP panel power during I2C initialization sequence · 0b5c541b
      Keith Packard authored
      The DP i2c initialization code does a couple of i2c transactions,
      which means that an eDP panel must be powered up.
      Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
      Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      0b5c541b