- 15 Mar, 2023 16 commits
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Hawking Zhang authored
Replace soc15, nv, soc21 specific callbacks with common one. so we don't need to duplicate code when introduce new asics. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
amdgpu_ras_register_ras_block should always be invoked by ras_sw_init, where driver needs to check ras caps at ip level, instead of asic level. Signed-off-by:
Stanley Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Hawking Zhang authored
pcie_bif ras blocks needs to be initialized as early as possible to handle fatal error detected in hw_init phase. also align the pcie_bif ras sw_init with other ras blocks Signed-off-by:
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Hawking Zhang authored
To align with other IP blocks. Signed-off-by:
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Hawking Zhang authored
To align with other IP blocks Signed-off-by:
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David Belanger authored
Handle case when module is unloaded (kfd_exit) before a process space (mm_struct) is released. v2: Fixed potential race conditions by removing all kfd_process from the process table first, then working on releasing the resources. v3: Fixed loop element access / synchronization. Fixed extra empty lines. Signed-off-by:
David Belanger <david.belanger@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along the following: - FW Release 0.0.158.0 - Fixes to HDCP, DP MST and more - Improvements on USB4 links and more - Code re-architecture on link.h Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
[Why & How] Add boot control bit to control dispclk and dppclk deep sleep Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Samson Tam authored
[Why & How] Reversed assert condition when checking that phy_pix_clk[] is not 0 Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Stylon Wang authored
[Why] The log "DMUB HPD callback" is crucial to identify when DP tunneling is been established and driver is notified of this event from DMUB. Same log is shared for long and short hotplug event and we need to check trailing DC debug log to distinguish between them two, making debugging on DPIA related issues a bit more troublesome. [How] Clearly states in dmesg logs whether this is a long or short hotplug event. Reviewed-by:
Hamza Mahfooz <Hamza.Mahfooz@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
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Wesley Chalmers authored
[Why & How] Make DCN32 functions available for more DCNs. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by:
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Yifan Zha authored
[Why] If disable the mmhub vm contexts(set MMVM_CONTEXTS_DISABLE to 0xffff), driver loading failed on vf due to fence fallback timer expired on all rings. FLR cannot reset MMVM_CONTEXTS_DISABLE. So this vf can not be recovered anymore unless trigger a whole gpu reset. [How] Under SRIOV, init MMVM_CONTEXTS_DISABLE in gmc11 golden register setting. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Reviewed-by:
Horace Chen <Horace.Chen@amd.com> Signed-off-by:
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Samson Tam authored
[Why] For dual displays where pixel rate is much higher on one display, we may get underflow when DET is evenly allocated. [How] Allocate less DET segments for the lower pixel rate display and more DET segments for the higher pixel rate display Reviewed-by:
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Ayush Gupta authored
[Why] Framedrops are observed while playing Vp9 and Av1 10 bit video on 8k resolution using VSR while playback controls are disappeared/appeared [How] Now ODM 2 to 1 is disabled for 5k or greater resolutions on VSR. Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Ayush Gupta <ayugupta@amd.com> Tested-by:
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Cruise Hung authored
[Why] In USB4 DP tunneling, it's possible to have this scenario that the path becomes unavailable and CM tears down the path a little bit late. So, in this case, the HPD is high but fails to read any DPCD register. That causes the link connection type to be set to sst. And not all sinks are removed behind the MST branch. [How] Restore the link connection type if it fails to read DPCD register. Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
Cruise Hung <Cruise.Hung@amd.com> Tested-by:
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Robin Chen authored
[Why] This is the fix for the defect of commit ab144f0b ("drm/amd/display: Allow individual control of eDP hotplug support"). [How] To revise the default eDP hotplug setting and use the enum to git rid of the magic number for different options. Fixes: ab144f0b ("drm/amd/display: Allow individual control of eDP hotplug support") Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Robin Chen <robin.chen@amd.com> Tested-by:
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- 14 Mar, 2023 9 commits
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Wesley Chalmers authored
[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Fangzhi Zuo authored
8b/10b encoding needs to add 3% fec overhead into the pbn. In the Synapcis Cascaded MST hub, the first stage MST branch device needs the information to determine the timeslot count for the second stage MST branch device. Missing this overhead will leads to insufficient timeslot allocation. Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by:
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Mustapha Ghaddar authored
[WHY] To validate the BW used for DPIAs per HostRouter [HOW] Add the Validate function in C source file Reviewed-by:
Mustapha Ghaddar <mghaddar@amd.com> Tested-by:
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Saaem Rizvi authored
[WHY] Hot plugging and then hot unplugging leads to k1 and k2 values to change, as signal is detected as a virtual signal on hot unplug. Writing these values to OTG_PIXEL_RATE_DIV register might cause primary display to blank (known hw bug). [HOW] No longer write k1 and k2 values to register if signal is virtual, we have safe guards in place in the case that k1 and k2 is unassigned so that an unknown value is not written to the register either. Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by:
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Wenjing Liu authored
[Why & How] All dc subcomponents should call another dc component via function pointers stored in a component structure. This is part of dc coding convention since the beginning. The reason behind this is to improve encapsulation and polymorphism. The function contract is extracted into a single link service structure defined in link.h header file and implemented only in link_factory.c instead of spreading across multiple files in link component file structure. Reviewed-by:
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Zhikai Zhai authored
[WHY] The VBIOS select the black boundary mode when using auto scale mode. But it doesn't recover if there is no reset. [HOW] Clean the scaler boundary mode to default edge in the manual scale mode. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Zhikai Zhai <zhikai.zhai@amd.com> Tested-by:
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Alvin Lee authored
[Description] - For pipe harvesting cases we must use DPP inst instead of pipe index for DPP related programming Reviewed-by:
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Swapnil Patel authored
[why] Currently if invalid luminescence range is reported in edid, then the driver doesn't have default range to fallback to. [How] Add default range if, the range is 0. Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
Swapnil Patel <Swapnil.Patel@amd.com> Tested-by:
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Fangzhi Zuo authored
Traditional synaptics hub has one MST branch device without virtual dpcd. Synaptics cascaded hub has two chained MST branch devices. DSC decoding is performed via root MST branch device, instead of the second MST branch device. Reviewed-by:
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- 13 Mar, 2023 15 commits
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Guilherme G. Piccoli authored
The VCN firmware loading path enables the indirect SRAM mode if it's advertised as supported. We might have some cases of FW issues that prevents this mode to working properly though, ending-up in a failed probe. An example below, observed in the Steam Deck: [...] [drm] failed to load ucode VCN0_RAM(0x3A) [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0000) amdgpu 0000:04:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring vcn_dec_0 test failed (-110) [drm:amdgpu_device_init.cold [amdgpu]] *ERROR* hw_init of IP block <vcn_v3_0> failed -110 amdgpu 0000:04:00.0: amdgpu: amdgpu_device_ip_init failed amdgpu 0000:04:00.0: amdgpu: Fatal error during GPU init [...] Disabling the VCN block circumvents this, but it's a very invasive workaround that turns off the entire feature. So, let's add a quirk on VCN loading that checks for known problematic BIOSes on Vangogh, so we can proactively disable the indirect SRAM mode and allow the HW proper probe and VCN IP block to work fine. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2385 Fixes: 82132ecc ("drm/amdgpu: enable Vangogh VCN indirect sram mode") Cc: stable@vger.kernel.org Cc: James Zhu <James.Zhu@amd.com> Cc: Leo Liu <leo.liu@amd.com> Signed-off-by:
Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by:
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Hamza Mahfooz authored
We should be checking if drm_dp_dpcd_read() returns the size that we are asking it to read instead of just checking if it is greater than zero. So, compare the return value of drm_dp_dpcd_read() to the requested read size. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Alex Deucher authored
Copy paste error. Fixes: 38433412 ("drm/amdgpu/nv: don't expose AV1 if VCN0 is harvested") Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4454 Cc: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Acked-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Benjamin Cheng authored
When FB_DAMAGE_CLIPS are provided in a non-MPO scenario, the loop does not use the counter i. This causes the fill_dc_dity_rect() to always fill dirty_rects[0], causing graphical artifacts when a damage clip aware DRM client sends more than 1 damage clip. Instead, use the flip_addrs->dirty_rect_count which is incremented by fill_dc_dirty_rect() on a successful fill. Fixes: 30ebe415 ("drm/amd/display: add FB_DAMAGE_CLIPS support") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2453Signed-off-by:
Benjamin Cheng <ben@bcheng.me> Signed-off-by:
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Hawking Zhang authored
Initialize hdp ras block only when mmhub ip block supports ras features. Driver queries ras capabilities after early_init, ras block init needs to be moved to sw_init. Signed-off-by:
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Hawking Zhang authored
Initialize mmhub ras block only when mmhub ip block supports ras features. Driver queries ras capabilities after early_init, ras block init needs to be moved to sw_init. Signed-off-by:
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Hawking Zhang authored
Use default gfx ras_late_init callback for gfx ras block. Signed-off-by:
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Hawking Zhang authored
Initialize umc ras block only when umc ip block supports ras. Driver queries ras capabilities after early_init, ras block init needs to be moved to sw_init. Signed-off-by:
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Hawking Zhang authored
Initialize vcn ras block only when vcn ip block supports ras features. Driver queries ras capabilities after early_init, ras block init needs to be moved to sw_int. Signed-off-by:
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Hawking Zhang authored
Initialize jpeg ras block only when jpeg ip block supports ras features. Driver queries ras capabilities after early_init, ras block init needs to be moved to sw_int. Signed-off-by:
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Guchun Chen authored
Some amd asics having reliable hotplug support don't call drm_kms_helper_poll_init in driver init sequence. However, due to the unified suspend/resume path for all asics, because the output_poll_work->func is not set for these asics, a warning arrives when suspending. [ 90.656049] <TASK> [ 90.656050] ? console_unlock+0x4d/0x100 [ 90.656053] ? __irq_work_queue_local+0x27/0x60 [ 90.656056] ? irq_work_queue+0x2b/0x50 [ 90.656057] ? __wake_up_klogd+0x40/0x60 [ 90.656059] __cancel_work_timer+0xed/0x180 [ 90.656061] drm_kms_helper_poll_disable.cold+0x1f/0x2c [drm_kms_helper] [ 90.656072] amdgpu_device_suspend+0x81/0x170 [amdgpu] [ 90.656180] amdgpu_pmops_runtime_suspend+0xb5/0x1b0 [amdgpu] [ 90.656269] pci_pm_runtime_suspend+0x61/0x1b0 drm_kms_helper_poll_enable/disable is valid when poll_init is called in amdgpu code, which is only used in non DC path. So move such codes into non-DC path code to get rid of such warnings. v1: introduce use_kms_poll flag in amdgpu as the poll stuff check v2: use dc_enabled as the flag to simply code v3: move code into non DC path instead of relying on any flag Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2411 Fixes: a4e77172 ("drm/probe_helper: sort out poll_running vs poll_enabled") Reported-by:
Bert Karwatzki <spasswolf@web.de> Suggested-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Suggested-by:
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Guchun Chen authored
The convert from adev is redundant. Signed-off-by:
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Guchun Chen authored
pm_sysfs_en is overlapped with pm.sysfs_initialized, so drop it for simplifying code(no functional change). Signed-off-by:
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Marek Olšák authored
This will be used for performance investigations. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
[Why] On resume some displays are not ready for HDCP, so they will fail if we start the hdcp authentintication too soon. Add a delay so that the displays can be ready before we start. NOTE: Previoulsy this delay was set to 3 seconds but it was causing issues with compliance, 2 seconds should enough for compliance and the s3 resume case. [How] Change the Delay to 2 seconds. Reviewed-by:
Aurabindo Pillai <Aurabindo.Pillai@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Tested-by:
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