- 06 Apr, 2016 40 commits
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Andrew Pinski authored
On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become corrupted if it contains data for a non-current ASID. This patch implements the workaround (which invalidates the local icache when switching the mm) by using code patching. Signed-off-by:
Andrew Pinski <apinski@cavium.com> Signed-off-by:
David Daney <david.daney@cavium.com> Reviewed-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> (cherry picked from linux-next commit 104a0c02) [ dannf: dropped Documentation/ change to file that didn't exist in v4.4; Adjusted cpu errata numbers for v4.4 ] Signed-off-by:
dann frazier <dann.frazier@canonical.com> Signed-off-by:
Tim Gardner <tim.gardner@canonical.com>
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Tirumalesh Chalamarla authored
Due to Errata in ThunderX, HOST_IRQ_STAT should be cleared before leaving the interrupt handler. The patch attempts to satisfy the need. Changes from V2: - removed newfile - code is now under CONFIG_ARM64 Changes from V1: - Rebased on top of libata/for-4.6 - Moved ThunderX intr handler to new file tj: Minor adjustments to comments. Signed-off-by:Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> Signed-off-by:
Tejun Heo <tj@kernel.org> (cherry picked from commit d243bed3) Signed-off-by:
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Sunil Goutham authored
On Thunderx pass 1.x and pass2 due to a HW errata default CQ DROP_LEVEL of 0x80 is not sufficient to avoid CQ_WR_FULL Qset error when packets are being received at >20Mpps resulting in complete stall of packet reception. This patch will configure it to 0x100 which is what is expected by HW on Thunderx. On future passes of thunderx and other chips HW default/reset value will be 0x100 or higher hence not overwritten. Signed-off-by:
Jerin Jacob <jerin.jacob@caviumnetworks.com> Signed-off-by:
Sunil Goutham <sgoutham@cavium.com> Signed-off-by:
David S. Miller <davem@davemloft.net> (cherry picked from linux-next commit 4c0b6eaf) Signed-off-by:
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dann frazier authored
Signed-off-by:
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1543165Signed-off-by:
Andy Whitcroft <apw@canonical.com>
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1543165Signed-off-by:
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1543165Signed-off-by:
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1543165Signed-off-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 I missed this when cleaning up the vce pg handling. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Alberto Milone <alberto.milone@canonical.com> Signed-off-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Enable vce and uvd pg based on single set of pg flags. Reviewed-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Enable vce and uvd pg based on single set of pg flags. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 So they can be used by powerplay. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Leftover from radeon. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Needed to pass the cg and pg info to powerplay. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Not working reliably yet. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Not working reliably yet. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Not working reliably yet. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Not working reliably yet. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Don't do anything if the uvd cg flags are not set. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 It was already disabled elsewhere, make it offical. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Don't attempt to start/stop the vce block if pg is disabled. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Don't attempt to start/stop the uvd block if pg is disabled. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 We already query this at driver init, so use that info. Also handles virtualization cases. Reviewed-by:
monk liu <monk.liu@amd.com> Signed-off-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Pcie registers may not be available in a virtualized environment. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Allows the user to force the supported pcie gen and lane config on both the asic and the chipset. Useful for debugging pcie problems and for virtualization where we may not be able to query the pcie bridge caps. Default to: gen: chipset 1/2, asic 1/2/3 lanes: 1/2/4/8/16 v2: fix bare metal case Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Doesn't work properly yet. Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Sonny Jiang <sonny.jiang@amd.com> Signed-off-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 The smc doesn't handle it. Reviewed-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Enable CP register/instruction error interrupts. Useful for debugging command stream problems. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Enable CP register/instruction error interrupts. Useful for debugging command stream problems. Reviewed-by:
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Oded Gabbay authored
BugLink: http://bugs.launchpad.net/bugs/1546572Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by:
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Nicolai Hähnle authored
BugLink: http://bugs.launchpad.net/bugs/1546572 This fixes a race condition in the error case: since the pt bos have not necessarily been reserved in case of an error, we could move a pt bo that is currently in the middle of being evicted/moved by another process, which then resulted in a BUG_ON in ttm_bo_add_to_lru. Reviewed-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
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Amitoj Kaur Chawla authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Remove an unnecassary cast in the argument to kfree. Found using Coccinelle. The semantic patch used to find this is as follows: //<smpl> @@ type T; expression *f; @@ - kfree((T *)(f)); + kfree(f); //</smpl> Signed-off-by:
Amitoj Kaur Chawla <amitoj1606@gmail.com> Signed-off-by:
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Colin Ian King authored
BugLink: http://bugs.launchpad.net/bugs/1546572 amdgpu_amdkfd_gfx_7_get_functions and amdgpu_amdkfd_gfx_8_0_get_functions have no parameters, so use the normal void parameter convention to make them match their prototypes in the header file drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Rex Zhu authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Fix firmware init on Stoney when powerplay is enabled. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Don't init fbdev if we don't have connectors. E.g., if you have a PX laptop with the displays attached to an IGP with no driver support, you may end up with a blank screen rather than falling back to vesa, etc. Based on a similar radeon patch from Rob Clark. Signed-off-by:
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Rob Clark authored
BugLink: http://bugs.launchpad.net/bugs/1546572 This fixes an issue that was noticed on an optimus/prime laptop with a kernel that was old enough to not support the integrated intel gfx (which was driving all the outputs), but did have support for the discrete radeon gpu. The end result was not falling back to VESA and leaving the user with a black screen. (Plus it is kind of silly to create an framebuffer device if there are no outputs hooked up to the gpu.) Signed-off-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
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Matthew Dawson authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Found with lockdep while testing gpu reset. Reviewed-by:
Matthew Dawson <matthew@mjdsystems.ca> Signed-off-by:
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Christian König authored
BugLink: http://bugs.launchpad.net/bugs/1546572 That somehow got lost. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Acked-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Makes it clear to the user which power management path is in use. v2: make consistent with dpm Reviewed-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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Eric Huang authored
BugLink: http://bugs.launchpad.net/bugs/1546572 The two macros returns are values which probably are used in the expression of calculation. Without the brackets the result of the expression may be wrong. v2: agd: squash both patches together Reviewed-by:
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