- 26 Feb, 2020 21 commits
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Yong Zhao authored
When the queue creation failed, some resources were not freed. Fix it. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Yong Zhao authored
The previous code of calculating active CP queues is problematic if some SDMA queues are inactive. Fix that by counting CP queues directly. Signed-off-by:
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Yong Zhao authored
The queues represented in queue_bitmap are only CP queues. Signed-off-by:
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Yong Zhao authored
The name is easier to understand the code. Signed-off-by:
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Divya Shikre authored
Devices from Arcturus onwards will have their UUID exposed to Thunk. Adding neccessary functions to the kernel to propagate the uuid. Signed-off-by:
Divya Shikre <DivyaUday.Shikre@amd.com> Signed-off-by:
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Kent Russell authored
pp_funcs may not exist, while dpm may be enabled. This change ensures that KFD topology will report the same as pp_dpm_sclk, as the conditions for reporting them will be the same. Otherwise, we may see the issue where KFD reports "100MHz" in topology as the max speed, while DPM is working correctly. Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Rohit Khaire authored
This change disables programming of GCVM_L2_CNTL* regs on VF. Signed-off-by:
Rohit Khaire <Rohit.Khaire@amd.com> Reviewed-by:
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Daniel Vetter authored
It's the last user, and more importantly, it's the last non-legacy user of anything in drm_pci.c. The only tricky bit is the agp initialization. But a close look shows that radeon does not use the drm_agp midlayer (the main use of that is drm_bufs for legacy drivers), and instead could use the agp subsystem directly (like nouveau does already). Hence we can just pull this in too. A further step would be to entirely drop the use of drm_device->agp, but feels like too much churn just for this patch. Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Signed-off-by:
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Daniel Vetter authored
This doesn't do anything except auto-init drm_agp support when you call drm_get_pci_dev(). Which amdgpu stopped doing with commit b58c1131 Author: Alex Deucher <alexander.deucher@amd.com> Date: Fri Jun 2 17:16:31 2017 -0400 drm/amdgpu: drop deprecated drm_get_pci_dev and drm_put_dev No idea whether this was intentional or accidental breakage, but I guess anyone who manages to boot a this modern gpu behind an agp bridge deserves a price. A price I never expect anyone to ever collect :-) Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Xiaojie Yuan <xiaojie.yuan@amd.com> Cc: Evan Quan <evan.quan@amd.com> Cc: "Tianci.Yin" <tianci.yin@amd.com> Cc: "Marek Olšák" <marek.olsak@amd.com> Cc: Hans de Goede <hdegoede@redhat.com> Reviewed-by:
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Chen Zhou authored
This silences the following coccinelle warning: "WARNING: sum of probable bitmasks, consider |" Reviewed-by:
Chen Zhou <chenzhou10@huawei.com> Signed-off-by:
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YueHaibing authored
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubp.c: In function hubp21_set_vm_system_aperture_settings: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hubp.c:343:23: warning: variable mc_vm_apt_default set but not used [-Wunused-but-set-variable] It is never used, so remove it. Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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Tom St Denis authored
Write a 32-bit value of zero to disable GFXOFF and write a 32-bit value of non-zero to enable GFXOFF. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Nirmoy Das authored
amdgpu_ring_test_helper already handles ring->sched.ready correctly Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Christian König authored
Add update fences to the root PD while mapping BOs. Otherwise PDs freed during the mapping won't wait for updates to finish and can cause corruptions. v2: rebased on drm-misc-next Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Tested-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Nirmoy Das authored
cleanup amdgpu_ring_fini to check the prerequisites before changing ring->sched.ready Signed-off-by:
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John Clements authored
Check Arcturus SKU type to select I2C address of page retirement EEPROM Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Hawking Zhang authored
driver needs to take DF out Cstate before any DF register access. otherwise, the DF register may not be accessible. Signed-off-by:
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Hawking Zhang authored
centralize all the xgmi related function to amdgpu_xgmi.c Signed-off-by:
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Hawking Zhang authored
The helper function hides software smu and legacy powerplay implementation for DF Cstate control. Signed-off-by:
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Evan Quan authored
For those ASICs with DF Cstate management centralized to PMFW, TMR setup should be performed between pmfw loading and other non-psp firmwares loading. V2: skip possible SMU firmware reloading Signed-off-by:
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xinhui pan authored
No need to trigger eviction as the memory mapping will not be used anymore. All pt/pd bos share same resv, hence the same shared eviction fence. Everytime page table is freed, the fence will be signled and that cuases kfd unexcepted evictions. v2: squash in 32 bit fix CC: Christian König <christian.koenig@amd.com> CC: Felix Kuehling <felix.kuehling@amd.com> CC: Alex Deucher <alexander.deucher@amd.com> Acked-by:
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- 25 Feb, 2020 19 commits
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Yu-ting Shen authored
[Why] when changing display clock, SMU need to use power up DFS and use DENTIST to ramp DFS DID to switch target frequency before switching back to bypass. [How] fixed the minimum display clock to 100MHz, it's W/A the same with PCO. Signed-off-by:
Yu-ting Shen <Yu-ting.Shen@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Jaehyun Chung authored
[Why] System will crash when trying to access local sink in core_link_enable_stream in MST case. [How] Access patches directly from stream. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Reviewed-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
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George Shen authored
[Why] Underflow sometimes occurs during transition into MPO with stutter enabled. [How] When transitioning into MPO, disable stutter. Re-enable stutter within one frame. Signed-off-by:
George Shen <george.shen@amd.com> Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Sung Lee authored
[WHY] Currently clock table struct is very far down in the bounding box struct making it hard to find while debugging, especially when using the dal3dbgext. [HOW] Move it up so it is the first struct defined, and therefore much easier to find and access. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Yongqiang Sun authored
[Why] In some display configuration like 1080P monitor playing a 1080P video, if user use ALT+F4 to exit Movie and TV, there is a chance clocks are same only water mark changed. Current clock optimization machanism will result in water mark keeps high after exit Movie and TV app. [How] Return if watermark need to be optimized when doing program watermark, perform the optimization after. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Need to assign surface size rather than viewport size for surface size dml variable. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Alvin Lee authored
[Why] We need to update TTU properly if DRAMClockChangeWatermark changes. If TTU < DRAMClockChangeWatermark, we pstate won't be allowed and we will hang in some PSR cases. [How] Update TTU if DramClockChangeWatermark value increases (only if TTU was dependent on the watermark value on the DRAMClockChangeWatermark value in the first place). Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Michael Strauss authored
[WHY] RV2 and variants are indistinguishable by hw internal rev alone, need to be distinguishable in order to correctly set max vlevel. Previous detection change incorrectly checked for hw internal rev. [HOW] Use pci revision to check if RV2 or low power variant Correct a few overlapping ASICREV range checks Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] We want to be able to enable PSR on DMCUB, and fallback to DMCU when necessary. [How] Add infrastructure to enable and disable PSR on DMCUB. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
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Dmytro Laktyushkin authored
Update dcn20_populate_dml_pipes_from_context to correctly handle odm when no surface is provided. Signed-off-by:
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Peikang Zhang authored
[Why] DalMPVisualConfirm does not support FreeSync 2 ARGB2101010 which causes black visual confirm bar when playing HDR video on FreeSync 2 display in full screen mode [How] Added pink color for DalMPVisualConfirm on FreeSync 2 ARGB2101010 surface Signed-off-by:
Peikang Zhang <peikang.zhang@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Martin Leung authored
[Why] Previously implemented early_cr_pattern was link level but the whole asic should be affected. [How] - change old link flag to dc level - new bit in dc->work_arounds set by DM Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Jaehyun Chung authored
[Why] Some displays clear ignore MSA bit on mode change, which cause blackscreen when programming variable vtotals. Ignore MSA bit needs programming needs to be delayed or re-set to be retained. [How] Create patch to delay programming ignore MSA bit after unblanking stream. Signed-off-by:
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David Galiffi authored
[Why] A software workaround is required for all vendor-built cards on platform. [How] When performing DP link training, we must send TPS1 before DPCD:100h is written with the proper bit rate value. This change must be applies in ALL cases when LT happens. Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
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Sung Lee authored
[WHY] Not programming dto with same values causes test failures in DCN2 diags DPP tests. [HOW] This reverts commit 1b53e733. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Firmware state helps to debug sequence issues and hangs for DMCUB commands and we don't have an easy mechanism to dump it from the driver. [How] Add a debugfs entry to dump the current firmware state. Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Vladimir Stempen authored
[Why] Currently DAL programs negative slope for the last point of output transfer function curve. [How] Applying a check for the last PWL point for RGB values not to be smaller than previous. If smaller, initialize the last point values to a sum of previous PWL value and previous PWL delta; Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by:
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