- 18 Jul, 2022 5 commits
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Bryan O'Donoghue authored
The Venus clock frequencies are a copy/paste error from msm8916. Looking at the original clock-gcc-8936.c ftbl_gcc_venus0_vcodec0_clk defines we have: - 133 MHz - 200 MHz - 266 MHz These values are born out by the relevant qualcomm documentation for the msm8936/msm8939 Venus core performance levels. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220712125922.3461675-4-bryan.odonoghue@linaro.org
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Bryan O'Donoghue authored
Standard CCI bus clock clocks are 19.2 MHz and 37.5 MHz. We already define the 19.2 MHz but are missing the 37.5 MHz. See qcom kernel drivers/clk/qcom/clock-gcc-8936.c::ftbl_gcc_camss_cci_clk[] Signed-off-by:
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Bryan O'Donoghue authored
Adding a new item to this frequency table I see the existing indentation is incorrect. Fixes: 1664014e ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller") Signed-off-by:
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Bjorn Andersson authored
When a GDSC is found to be enabled at boot the pm_runtime state will be unbalanced as the GDSC is later turned off. Fix this by increasing the usage counter on the power-domain, in line with how we handled the regulator state. Fixes: 1b771839 ("clk: qcom: gdsc: enable optional power domain support") Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220713212818.130277-1-bjorn.andersson@linaro.org
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Abel Vesa authored
Both dispcc and videocc use mmcx power domain now. Lets drop the supply mmcx from every gdsc. Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: 266e5cf3 ("arm64: dts: qcom: sm8250: remove mmcx regulator") Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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- 17 Jul, 2022 1 commit
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Ren Zhijie authored
CONFIG_CC_VERSION_TEXT="x86_64-linux-gnu-gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0" make ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-, will be failed, like this: drivers/clk/qcom/gpucc-sm8350.c:111:2: error: initializer element is not constant gpu_cc_parent, ^~~~~~~~~~~~~ drivers/clk/qcom/gpucc-sm8350.c:111:2: note: (near initialization for ‘gpu_cc_parent_data_0[0]’) drivers/clk/qcom/gpucc-sm8350.c:126:2: error: initializer element is not constant gpu_cc_parent, ^~~~~~~~~~~~~ drivers/clk/qcom/gpucc-sm8350.c:126:2: note: (near initialization for ‘gpu_cc_parent_data_1[0]’) make[3]: *** [drivers/clk/qcom/gpucc-sm8350.o] Error 1 It seems that nested constant initializer is not supported in GCC 7.4.0. For portability resons, we should fix it. Reported-by:
Hulk Robot <hulkci@huawei.com> Fixes: 160758b0 ("clk: qcom: add support for SM8350 GPUCC") Signed-off-by:
Ren Zhijie <renzhijie2@huawei.com> Signed-off-by:
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- 06 Jul, 2022 13 commits
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Dmitry Baryshkov authored
Add additional GCC clock sources. This includes PCIe and USB PIPE and UFS symbol clocks. Fixes: 2a8aa18c ("dt-bindings: clk: qcom: Fix self-validation, split, and clean cruft") Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Jonathan Marek authored
Add support to the SM8350 display clock controller by extending the SM8250 display clock controller, which is almost identical but has some minor differences. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Signed-off-by:
Robert Foss <robert.foss@linaro.org> Reviewed-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Robert Foss authored
The GPUCC manages the clocks for the Adreno GPU found on the sm8350 SoCs. Signed-off-by:
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Bjorn Andersson authored
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Vladimir Zapolskiy authored
Add camera clock controller driver found on Qualcomm SM8450 SoC. Reviewed-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by:
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Vladimir Zapolskiy authored
Add and export Rivian EVO PLL configuration and control functions to clock controller drivers, the PLL is used by SM8450 camera clock controller. Reviewed-by:
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Vladimir Zapolskiy authored
Add controls for Lucid EVO PLL configuration and export control functions to clock controller drivers, the PLL is used by Qualcomm SM8450 camera and display clock controllers. Reviewed-by:
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Vladimir Zapolskiy authored
Unify all exported PLL clock configuration functions and data structures as GPL symbols. Reviewed-by:
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Vladimir Zapolskiy authored
After merging lucid and trion pll functions in commit 0b014894 ("clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid") the function clk_trion_pll_configure() is left with an old description header, which results in a W=2 compile time warning, fix it. Acked-by:
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Bjorn Andersson authored
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Vladimir Zapolskiy authored
The change adds device tree bindings for camera clock controller found on SM8450 SoC. Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Jonathan Marek authored
Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 bindings. Update the documentation with the new compatible. Signed-off-by:
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Robert Foss authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by:
Dmitry Baryshkov <dmityr.baryshkov@linaro.org> Reviewed-by:
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- 05 Jul, 2022 3 commits
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Dmitry Baryshkov authored
Currently gcc-msm8960 driver manually creates tsens platform device manually. It would be better to follow IPQ8064 approach, where tsens device is defined as gcc's child device in the device tree. If nothing else, it removes gcc's dependency on QFPROM, thus allowing clock controller to be probed earlier. Don't create it in case there are available child nodes (tsens) inside the gcc's device tree node. Signed-off-by:
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Dmitry Baryshkov authored
Split tsens properties to the child node of the gcc. This follows the lead of ipq8064 (which also uses a separate node for tsens) and makes device tree closer to other platforms, where tsens is a completely separate device. Signed-off-by:
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Dmitry Baryshkov authored
MSM8960 shares the design (and the driver) of the global clock controller with APQ8064. Move it from clock/qcom,gcc-other.yaml to clock/qcom,gcc-apq8064.yaml. As the example in gcc-other.yaml was using qcom,gcc-msm8960 compat string, change it to qcom,gcc-msm8974. Reviewed-by:
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- 01 Jul, 2022 3 commits
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Nikita Travkin authored
msm8916 has (at least) 6 "General Purpose" clocks that can be muxed to SoC pins. These clocks are: GP_CLK{0, 1} : GPIO_{31, 32} (Belongs to CAMSS according to Linux) GP_CLK_{1-3}{A, B} : GPIO_{49-51, 97, 12, 13} (Belongs to GCC itself) GP_MN : GPIO_110 (Doesn't seem to be described in gcc, ignored in this patch) Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them. Reviewed-by:Nikita Travkin <nikita@trvn.ru> Signed-off-by:
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Nikita Travkin authored
Sometimes calculation of d value may result in 0 because of the rounding after integer division. This causes the following error: [ 113.969689] camss_gp1_clk_src: rcg didn't update its configuration. [ 113.969754] WARNING: CPU: 3 PID: 35 at drivers/clk/qcom/clk-rcg2.c:122 update_config+0xc8/0xdc Make sure that D value is never zero. Fixes: 7f891faf ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG") Signed-off-by:
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Nikita Travkin authored
In cases when MND is not enabled (e.g. when only Half Integer Divider is used), setting D registers makes no effect. Fail instead of making ineffective write. Fixes: 7f891faf ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG") Signed-off-by:
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- 30 Jun, 2022 15 commits
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Vladimir Zapolskiy authored
On SM8250 two found VFE GDSC power domains shall not be operated, if titan top is turned off, thus the former power domains will be set as subdomains by a GDSC registration routine. Fixes: 5d66ca79 ("clk: qcom: Add camera clock controller driver for SM8250") Signed-off-by:
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Vladimir Zapolskiy authored
On SDM845 two found VFE GDSC power domains shall not be operated, if titan top is turned off, thus the former power domains will be set as subdomains by a GDSC registration routine. Fixes: 78412c26 ("clk: qcom: Add camera clock controller driver for SDM845") Signed-off-by:
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Robert Marko authored
Once the usb sleep clocks are disabled, clock framework is trying to disable the sleep clock source also. However, it seems that it cannot be disabled and trying to do so produces: [ 245.436390] ------------[ cut here ]------------ [ 245.441233] gcc_sleep_clk_src status stuck at 'on' [ 245.441254] WARNING: CPU: 2 PID: 223 at clk_branch_wait+0x130/0x140 [ 245.450435] Modules linked in: xhci_plat_hcd xhci_hcd dwc3 dwc3_qcom leds_gpio [ 245.456601] CPU: 2 PID: 223 Comm: sh Not tainted 5.18.0-rc4 #215 [ 245.463889] Hardware name: Xiaomi AX9000 (DT) [ 245.470050] pstate: 204000c5 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 245.474307] pc : clk_branch_wait+0x130/0x140 [ 245.481073] lr : clk_branch_wait+0x130/0x140 [ 245.485588] sp : ffffffc009f2bad0 [ 245.489838] x29: ffffffc009f2bad0 x28: ffffff8003e6c800 x27: 0000000000000000 [ 245.493057] x26: 0000000000000000 x25: 0000000000000000 x24: ffffff800226ef20 [ 245.500175] x23: ffffffc0089ff550 x22: 0000000000000000 x21: ffffffc008476ad0 [ 245.507294] x20: 0000000000000000 x19: ffffffc00965ac70 x18: fffffffffffc51a7 [ 245.514413] x17: 68702e3030303837 x16: 3a6d726f6674616c x15: ffffffc089f2b777 [ 245.521531] x14: ffffffc0095c9d18 x13: 0000000000000129 x12: 0000000000000129 [ 245.528649] x11: 00000000ffffffea x10: ffffffc009621d18 x9 : 0000000000000001 [ 245.535767] x8 : 0000000000000001 x7 : 0000000000017fe8 x6 : 0000000000000001 [ 245.542885] x5 : ffffff803fdca6d8 x4 : 0000000000000000 x3 : 0000000000000027 [ 245.550002] x2 : 0000000000000027 x1 : 0000000000000023 x0 : 0000000000000026 [ 245.557122] Call trace: [ 245.564229] clk_branch_wait+0x130/0x140 [ 245.566490] clk_branch2_disable+0x2c/0x40 [ 245.570656] clk_core_disable+0x60/0xb0 [ 245.574561] clk_core_disable+0x68/0xb0 [ 245.578293] clk_disable+0x30/0x50 [ 245.582113] dwc3_qcom_remove+0x60/0xc0 [dwc3_qcom] [ 245.585588] platform_remove+0x28/0x60 [ 245.590361] device_remove+0x4c/0x80 [ 245.594179] device_release_driver_internal+0x1dc/0x230 [ 245.597914] device_driver_detach+0x18/0x30 [ 245.602861] unbind_store+0xec/0x110 [ 245.607027] drv_attr_store+0x24/0x40 [ 245.610847] sysfs_kf_write+0x44/0x60 [ 245.614405] kernfs_fop_write_iter+0x128/0x1c0 [ 245.618052] new_sync_write+0xc0/0x130 [ 245.622391] vfs_write+0x1d4/0x2a0 [ 245.626123] ksys_write+0x58/0xe0 [ 245.629508] __arm64_sys_write+0x1c/0x30 [ 245.632895] invoke_syscall.constprop.0+0x5c/0x110 [ 245.636890] do_el0_svc+0xa0/0x150 [ 245.641488] el0_svc+0x18/0x60 [ 245.644872] el0t_64_sync_handler+0xa4/0x130 [ 245.647914] el0t_64_sync+0x174/0x178 [ 245.652340] ---[ end trace 0000000000000000 ]--- So, add CLK_IS_CRITICAL flag to the clock so that the kernel won't try to disable the sleep clock. Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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Robert Marko authored
Add GDSC-s for each of the two USB controllers built-in the IPQ8074. Signed-off-by:
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Bjorn Andersson authored
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Robert Marko authored
Add bindings for the USB GDSCs found in IPQ8074 GCC. Signed-off-by:
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Robert Marko authored
GCC inside of IPQ8074 also provides power management via built-in GDSCs. In order to do so, '#power-domain-cells' must be set to 1. Signed-off-by:
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Robert Marko authored
Currently, attempting to enable the UBI clocks will cause the stuck at off warning to be printed and clk_enable will fail. [ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off' Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY flag on UBI clocks, so lets do the same. Fixes: 5736294a ("clk: qcom: ipq8074: add NSS clocks") Signed-off-by:
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Robert Marko authored
The built-in PPE engine has a dedicated clock for the EIP-197 crypto engine. So, since the required clock currently missing add support for it. Signed-off-by:
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Robert Marko authored
Add binding for the PPE crypto clock in IPQ8074. Signed-off-by:
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Robert Marko authored
NSS port 5 and 6 frequency tables are currently broken and are causing a wide ranges of issue like 1G not working at all on port 6 or port 5 being clocked with 312 instead of 125 MHz as UNIPHY1 gets selected. So, update the frequency tables with the ones from the downstream QCA 5.4 based kernel which has already fixed this. Fixes: 7117a51e ("clk: qcom: ipq8074: add NSS ethernet port clocks") Signed-off-by:
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Robert Marko authored
UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it will cause the wait_for_pll() to timeout and thus return the error indicating that the PLL failed to lock. This is bug in Huayra PLL HW for which SW workaround is to set bit 26 of TEST_CTL register. This is ported from the QCA 5.4 based downstream kernel. Fixes: b8e7e519 ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by:
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Robert Marko authored
Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration to work. So, obtain the regmap that is required for the Alpha PLL configuration and thus utilize the qcom_cc_really_probe() as we already have the regmap. Then utilize the Alpha PLL configs from the downstream QCA 5.4 based kernel to configure them. This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the kernel. Fixes: b8e7e519 ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by:
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Bryan O'Donoghue authored
Qcom docs indciate the following peripherals operating from System NOC MM not from System NOC clocks. - MDP - VFE - JPEGe - Venus Switch over the relevant parent pointers. Fixes: 1664014e ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller") Signed-off-by:
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Bryan O'Donoghue authored
The msm8939 has an additional higher operating point for the multi-media peripherals. The higher throughput MM componets operate off of the system-mm noc not the system noc. system_mm_noc_bfdcd_clk_src is the source clock for the higher frequency capable system noc mm. Maximum frequency for the MM SNOC is 400 MHz. Fixes: 1664014e ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller") Signed-off-by:
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