1. 12 Dec, 2005 36 commits
  2. 09 Dec, 2005 4 commits
    • Kazunori MIYAZAWA's avatar
      [IPv6] IPsec: fix pmtu calculation of esp · 73d4f84f
      Kazunori MIYAZAWA authored
      It is a simple bug which uses the wrong member.
      
      This bug does not seriously affect ordinary use of IPsec.
      But it is important to pass IPv6 ready logo phase-2
      conformance test of IPsec SGW.
      Signed-off-by: default avatarKazunori MIYAZAWA <miyazawa@linux-ipv6.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      73d4f84f
    • David Gibson's avatar
      [PATCH] powerpc: Fix SLB flushing path in hugepage · 23ed6cb9
      David Gibson authored
      On ppc64, when opening a new hugepage region, we need to make sure any
      old normal-page SLBs for the area are flushed on all CPUs.  There was
      a bug in this logic - after putting the new hugepage area masks into
      the thread structure, we copied it into the paca (read by the SLB miss
      handler) only on one CPU, not on all.  This could cause incorrect SLB
      entries to be loaded when a multithreaded program was running
      simultaneously on several CPUs.  This patch corrects the error,
      copying the context information into the PACA on all CPUs using the mm
      in question before flushing any existing SLB entries.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      23ed6cb9
    • David Gibson's avatar
      [PATCH] powerpc: Add missing icache flushes for hugepages · cbf52afd
      David Gibson authored
      On most powerpc CPUs, the dcache and icache are not coherent so
      between writing and executing a page, the caches must be flushed.
      Userspace programs assume pages given to them by the kernel are icache
      clean, so we must do this flush between the kernel clearing a page and
      it being mapped into userspace for execute.  We were not doing this
      for hugepages, this patch corrects the situation.
      
      We use the same lazy mechanism as we use for normal pages, delaying
      the flush until userspace actually attempts to execute from the page
      in question.
      
      Tested on G5.
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      cbf52afd
    • Olof Johansson's avatar
      [PATCH] powerpc: Set cache info defaults · dabcafd3
      Olof Johansson authored
      Cache info is setup by walking the device tree in initialize_cache_info().
      However, icache_flush_range might be called before that, in
      slb_initialize()->patch_slb_encoding, which modifies the load immediate
      instructions used with SLB fault code.
      
      Not only that, but depending on memory layout, we might take SLB faults
      during unflatten_device_tree. So that fault will load an SLB entry that
      might not contain the right LLP flags for the segment.
      
      Either we can walk the flattened device tree to setup cache info, or
      we can pick the known defaults that are known to work. Doing it in the
      flattened device tree is hairier since we need to know the machine type
      to know what property to look for, etc, etc.
      
      For now, it's just easier to go with the defaults. Worst thing that
      happens from it is that we might waste a few cycles doing too small
      dcbst/icbi increments.
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      dabcafd3