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  1. 07 May, 2011 4 commits
  3. 03 May, 2011 27 commits
  5. 02 May, 2011 9 commits
    • Anatolij Gustschin's avatar
      USB: extend ehci-fsl and fsl_udc_core driver for OTG operation · 83722bc9
      Anatolij Gustschin authored 
      Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
Cc: Li Yang <leoli@freescale.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      83722bc9
    • Li Yang's avatar
      USB: add Freescale USB OTG Transceiver driver · 0807c500
      Li Yang authored 
      Slightly reworked and cleaned up driver from Freescale LTIB
for MPC5121E. The driver has been ported to the current kernel,
proc interface "/proc/driver/fsl_usb2_otg" has been replaced by
sysfs interface.
Signed-off-by: default avatarLi Yang <leoli@freescale.com>
Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      0807c500
    • Anatolij Gustschin's avatar
      USB: fsl_udc_core: support device mode of MPC5121E DR USB Controller · 2ea6698d
      Anatolij Gustschin authored 
      Extend the FSL UDC driver to support MPC5121E DR USB Controller
operation in device mode. Add MPC5121E specific init/uninit
at probe and remove and isolate system interface register accesses
when running on MPC5121E SoC, as these registers are not available
on this platform. This patch relies on previous patch for supporting
big endian registers and descriptors access in the FSL UDC driver.
Additionally support endpoint FIFO status operation by providing
appropriate callback in endpoint ops structure.

Also flush cache for the req buffer used for GetStatus reply.
Without this, the correct reply to an endpoint GetStatus
is written to 'req', but doesn't make it out to the USB bus
since the buffer hasn't been flushed. This would cause the
USBCV Halt Endpoint test to fail (according to changelog in
Freescale LTIB driver code).
Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
Cc: Li Yang <leoli@freescale.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      2ea6698d
    • Anatolij Gustschin's avatar
      USB: fsl_udc_core: prepare for SoCs with BE registers and descriptors · 09ba0def
      Anatolij Gustschin authored 
      On some SoCs, the USB controller registers and descriptors can be big
or little endian, depending on the version of the chip. In order to be
able to run the same kernel binary on different versions of an SoC, the
BE/LE decision must be made at run time. Provide appropriate register
and descriptor accessors which are configurable at run time using the
configuration flags from fsl_usb2_platform_data data structure.

This is in preparation for adding support for MPC5121E DR USB2 Controller
to the FSL UDC driver.
Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
Cc: Li Yang <leoli@freescale.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      09ba0def
    • Anatolij Gustschin's avatar
      USB: fix build of FSL MPH DR OF platform driver · b703e47e
      Anatolij Gustschin authored 
      When only FSL USB gadget driver is selected in the kernel
configuration the MPH DR OF driver for creation of FSL
USB platform devices from device tree won't be built.
As a result no USB platform devices for MPH DR USB controller
will be created at run time and no probing will be done in
the fsl_udc_core driver.

Add an entry to the Makefile to build the MPH DR OF
platform driver if CONFIG_USB_FSL_MPH_DR_OF is defined.
Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      b703e47e
    • Anatolij Gustschin's avatar
      USB: ehci-fsl: add MPC5121E specific suspend and resume · 13b7ee2a
      Anatolij Gustschin authored 
      Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      13b7ee2a
    • Sarah Sharp's avatar
      xhci 1.0: Set transfer burst last packet count field. · b61d378f
      Sarah Sharp authored 
      The xHCI 1.0 specification defines a new isochronous TRB field, called
transfer burst last packet count (TBLPC).  This field defines the number
of packets in the last "burst" of packets in a TD.  Only SuperSpeed
endpoints can handle more than one burst, so this is set to the number for
packets in a TD for all non-SuperSpeed devices (minus one, since the field
is zero based).

This patch should have no effect on host controllers that don't advertise
the xHCI 1.0 (0x100) version number in their hci_version field.
Signed-off-by: default avatarSarah Sharp <sarah.a.sharp@linux.intel.com>
      b61d378f
    • Sarah Sharp's avatar
      xhci 1.0: Set transfer burst count field. · 5cd43e33
      Sarah Sharp authored 
      The xHCI 1.0 specification adds a new field to the fourth dword in an
isochronous TRB: the transfer burst count (TBC).  This field is only
non-zero for SuperSpeed devices.  Each SS endpoint sets the bMaxBurst
field in the SuperSpeed endpoint companion descriptor, which indicates how
many max-packet-sized "bursts" it can handle in one service interval.  The
device driver may choose to burst less max packet sized chunks each
service interval (which is defined by one TD).  The xHCI driver indicates
to the host controller how many bursts it needs to schedule through the
transfer burst count field.

This patch will only effect xHCI hosts that advertise 1.0 support (0x100)
in the HCI version field of their capabilities register.
Signed-off-by: default avatarSarah Sharp <sarah.a.sharp@linux.intel.com>
      5cd43e33
    • Sarah Sharp's avatar
      xhci 1.0: Update TD size field format. · 4da6e6f2
      Sarah Sharp authored 
      The xHCI 1.0 specification changes the format of the TD size field in
Normal and Isochronous TRBs.  The field in control TRBs is still set to
reserved zero.  Instead of representing the number of bytes left to
transfer in the TD (including the current TRB's buffer), it now represents
the number of packets left to transfer (*not* including this TRB).

See section 4.11.2.4 of the xHCI 1.0 specification for details.  The math
is basically copied straight from there.

Create a new function, xhci_v1_0_td_remainder(), that should be called for
all xHCI 1.0 host controllers.  The field location and maximum value is
still the same, so reuse the old function, xhci_td_remainder(), to handle
the bit shifting.
Signed-off-by: default avatarSarah Sharp <sarah.a.sharp@linux.intel.com>
      4da6e6f2
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