1. 23 Jan, 2020 8 commits
    • Jerónimo Borque's avatar
      USB: serial: simple: Add Motorola Solutions TETRA MTP3xxx and MTP85xx · 69874bf1
      Jerónimo Borque authored
      commit 260e41ac upstream.
      
      Add device-ids for the Motorola Solutions TETRA radios MTP3xxx series
      and MTP85xx series
      
      $ lsusb -vd 0cad:
      
      Bus 001 Device 009: ID 0cad:9015 Motorola CGISS TETRA PEI interface
      Device Descriptor:
        bLength                18
        bDescriptorType         1
        bcdUSB               2.00
        bDeviceClass            0
        bDeviceSubClass         0
        bDeviceProtocol         0
        bMaxPacketSize0        64
        idVendor           0x0cad Motorola CGISS
        idProduct          0x9015
        bcdDevice           24.16
        iManufacturer           1
        iProduct                2
        iSerial                 0
        bNumConfigurations      1
        Configuration Descriptor:
          bLength                 9
          bDescriptorType         2
          wTotalLength       0x0037
          bNumInterfaces          2
          bConfigurationValue     1
          iConfiguration          3
          bmAttributes         0x80
            (Bus Powered)
          MaxPower              500mA
          Interface Descriptor:
            bLength                 9
            bDescriptorType         4
            bInterfaceNumber        0
            bAlternateSetting       0
            bNumEndpoints           2
            bInterfaceClass       255 Vendor Specific Class
            bInterfaceSubClass      0
            bInterfaceProtocol      0
            iInterface              0
            Endpoint Descriptor:
              bLength                 7
              bDescriptorType         5
              bEndpointAddress     0x81  EP 1 IN
              bmAttributes            2
                Transfer Type            Bulk
                Synch Type               None
                Usage Type               Data
              wMaxPacketSize     0x0040  1x 64 bytes
              bInterval               0
            Endpoint Descriptor:
              bLength                 7
              bDescriptorType         5
              bEndpointAddress     0x01  EP 1 OUT
              bmAttributes            2
                Transfer Type            Bulk
                Synch Type               None
                Usage Type               Data
              wMaxPacketSize     0x0040  1x 64 bytes
              bInterval               0
          Interface Descriptor:
            bLength                 9
            bDescriptorType         4
            bInterfaceNumber        1
            bAlternateSetting       0
            bNumEndpoints           2
            bInterfaceClass       255 Vendor Specific Class
            bInterfaceSubClass      0
            bInterfaceProtocol      0
            iInterface              0
            Endpoint Descriptor:
              bLength                 7
              bDescriptorType         5
              bEndpointAddress     0x82  EP 2 IN
              bmAttributes            2
                Transfer Type            Bulk
                Synch Type               None
                Usage Type               Data
              wMaxPacketSize     0x0040  1x 64 bytes
              bInterval               0
            Endpoint Descriptor:
              bLength                 7
              bDescriptorType         5
              bEndpointAddress     0x02  EP 2 OUT
              bmAttributes            2
                Transfer Type            Bulk
                Synch Type               None
                Usage Type               Data
              wMaxPacketSize     0x0040  1x 64 bytes
              bInterval               0
      
      Bus 001 Device 010: ID 0cad:9013 Motorola CGISS TETRA PEI interface
      Device Descriptor:
        bLength                18
        bDescriptorType         1
        bcdUSB               2.00
        bDeviceClass            0
        bDeviceSubClass         0
        bDeviceProtocol         0
        bMaxPacketSize0        64
        idVendor           0x0cad Motorola CGISS
        idProduct          0x9013
        bcdDevice           24.16
        iManufacturer           1
        iProduct                2
        iSerial                 0
        bNumConfigurations      1
        Configuration Descriptor:
          bLength                 9
          bDescriptorType         2
          wTotalLength       0x0037
          bNumInterfaces          2
          bConfigurationValue     1
          iConfiguration          3
          bmAttributes         0x80
            (Bus Powered)
          MaxPower              500mA
          Interface Descriptor:
            bLength                 9
            bDescriptorType         4
            bInterfaceNumber        0
            bAlternateSetting       0
            bNumEndpoints           2
            bInterfaceClass       255 Vendor Specific Class
            bInterfaceSubClass      0
            bInterfaceProtocol      0
            iInterface              0
            Endpoint Descriptor:
              bLength                 7
              bDescriptorType         5
              bEndpointAddress     0x81  EP 1 IN
              bmAttributes            2
                Transfer Type            Bulk
                Synch Type               None
                Usage Type               Data
              wMaxPacketSize     0x0200  1x 512 bytes
              bInterval               0
            Endpoint Descriptor:
              bLength                 7
              bDescriptorType         5
              bEndpointAddress     0x01  EP 1 OUT
              bmAttributes            2
                Transfer Type            Bulk
                Synch Type               None
                Usage Type               Data
              wMaxPacketSize     0x0200  1x 512 bytes
              bInterval               0
          Interface Descriptor:
            bLength                 9
            bDescriptorType         4
            bInterfaceNumber        1
            bAlternateSetting       0
            bNumEndpoints           2
            bInterfaceClass       255 Vendor Specific Class
            bInterfaceSubClass      0
            bInterfaceProtocol      0
            iInterface              0
            Endpoint Descriptor:
              bLength                 7
              bDescriptorType         5
              bEndpointAddress     0x82  EP 2 IN
              bmAttributes            2
                Transfer Type            Bulk
                Synch Type               None
                Usage Type               Data
              wMaxPacketSize     0x0200  1x 512 bytes
              bInterval               0
            Endpoint Descriptor:
              bLength                 7
              bDescriptorType         5
              bEndpointAddress     0x02  EP 2 OUT
              bmAttributes            2
                Transfer Type            Bulk
                Synch Type               None
                Usage Type               Data
              wMaxPacketSize     0x0200  1x 512 bytes
              bInterval               0
      Signed-off-by: default avatarJerónimo Borque <jeronimo@borque.com.ar>
      Cc: stable <stable@vger.kernel.org>
      Signed-off-by: default avatarJohan Hovold <johan@kernel.org>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      69874bf1
    • Lars Möllendorf's avatar
      iio: buffer: align the size of scan bytes to size of the largest element · e5d1fe94
      Lars Möllendorf authored
      commit 883f6165 upstream.
      
      Previous versions of `iio_compute_scan_bytes` only aligned each element
      to its own length (i.e. its own natural alignment). Because multiple
      consecutive sets of scan elements are buffered this does not work in
      case the computed scan bytes do not align with the natural alignment of
      the first scan element in the set.
      
      This commit fixes this by aligning the scan bytes to the natural
      alignment of the largest scan element in the set.
      
      Fixes: 959d2952 ("staging:iio: make iio_sw_buffer_preenable much more general.")
      Signed-off-by: default avatarLars Möllendorf <lars.moellendorf@plating.de>
      Reviewed-by: default avatarLars-Peter Clausen <lars@metafoo.de>
      Cc: <Stable@vger.kernel.org>
      Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      e5d1fe94
    • Stephan Gerhold's avatar
      ASoC: msm8916-wcd-digital: Reset RX interpolation path after use · 7acabcf1
      Stephan Gerhold authored
      commit 85578bbd upstream.
      
      For some reason, attempting to route audio through QDSP6 on MSM8916
      causes the RX interpolation path to get "stuck" after playing audio
      a few times. In this situation, the analog codec part is still working,
      but the RX path in the digital codec stops working, so you only hear
      the analog parts powering up. After a reboot everything works again.
      
      So far I was not able to reproduce the problem when using lpass-cpu.
      
      The downstream kernel driver avoids this by resetting the RX
      interpolation path after use. In mainline we do something similar
      for the TX decimator (LPASS_CDC_CLK_TX_RESET_B1_CTL), but the
      interpolator reset (LPASS_CDC_CLK_RX_RESET_CTL) got lost when the
      msm8916-wcd driver was split into analog and digital.
      
      Fix this problem by adding the reset to
      msm8916_wcd_digital_enable_interpolator().
      
      Fixes: 150db8c5 ("ASoC: codecs: Add msm8916-wcd digital codec")
      Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Signed-off-by: default avatarStephan Gerhold <stephan@gerhold.net>
      Link: https://lore.kernel.org/r/20200105102753.83108-1-stephan@gerhold.netSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      7acabcf1
    • Guenter Roeck's avatar
      clk: Don't try to enable critical clocks if prepare failed · 5f047e38
      Guenter Roeck authored
      commit 12ead774 upstream.
      
      The following traceback is seen if a critical clock fails to prepare.
      
      bcm2835-clk 3f101000.cprman: plld: couldn't lock PLL
      ------------[ cut here ]------------
      Enabling unprepared plld_per
      WARNING: CPU: 1 PID: 1 at drivers/clk/clk.c:1014 clk_core_enable+0xcc/0x2c0
      ...
      Call trace:
       clk_core_enable+0xcc/0x2c0
       __clk_register+0x5c4/0x788
       devm_clk_hw_register+0x4c/0xb0
       bcm2835_register_pll_divider+0xc0/0x150
       bcm2835_clk_probe+0x134/0x1e8
       platform_drv_probe+0x50/0xa0
       really_probe+0xd4/0x308
       driver_probe_device+0x54/0xe8
       device_driver_attach+0x6c/0x78
       __driver_attach+0x54/0xd8
      ...
      
      Check return values from clk_core_prepare() and clk_core_enable() and
      bail out if any of those functions returns an error.
      
      Cc: Jerome Brunet <jbrunet@baylibre.com>
      Fixes: 99652a46 ("clk: migrate the count of orphaned clocks at init")
      Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
      Link: https://lkml.kernel.org/r/20191225163429.29694-1-linux@roeck-us.netSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      5f047e38
    • Alexandre Belloni's avatar
      ARM: dts: imx6q-dhcom: fix rtc compatible · 8e1d9fc9
      Alexandre Belloni authored
      commit 7d7778b1 upstream.
      
      The only correct and documented compatible string for the rv3029 is
      microcrystal,rv3029. Fix it up.
      
      Fixes: 52c7a088 ("ARM: dts: imx6q: Add support for the DHCOM iMX6 SoM and PDK2")
      Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
      Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      8e1d9fc9
    • Martin Blumenstingl's avatar
      dt-bindings: reset: meson8b: fix duplicate reset IDs · 09714577
      Martin Blumenstingl authored
      commit 4881873f upstream.
      
      According to the public S805 datasheet the RESET2 register uses the
      following bits for the PIC_DC, PSC and NAND reset lines:
      - PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
      - PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
      - NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)
      
      Update the reset IDs of these three reset lines so they don't conflict
      with PIC_DC and map to the actual hardware reset lines.
      
      Fixes: 79795e20 ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller")
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      09714577
    • Georgi Djakov's avatar
      clk: qcom: gcc-sdm845: Add missing flag to votable GDSCs · d8a82587
      Georgi Djakov authored
      commit 5e82548e upstream.
      
      On sdm845 devices, during boot we see the following warnings (unless we
      have added 'pd_ignore_unused' to the kernel command line):
      	hlos1_vote_mmnoc_mmu_tbu_sf_gdsc status stuck at 'on'
      	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc status stuck at 'on'
      	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc status stuck at 'on'
      	hlos1_vote_aggre_noc_mmu_tbu2_gdsc status stuck at 'on'
      	hlos1_vote_aggre_noc_mmu_tbu1_gdsc status stuck at 'on'
      	hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc status stuck at 'on'
      	hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc status stuck at 'on'
      
      As the name of these GDSCs suggests, they are "votable" and in downstream
      DT, they all have the property "qcom,no-status-check-on-disable", which
      means that we should not poll the status bit when we disable them.
      
      Luckily the VOTABLE flag already exists and it does exactly what we need,
      so let's make use of it to make the warnings disappear.
      
      Fixes: 06391edd ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
      Reported-by: default avatarRob Clark <robdclark@gmail.com>
      Signed-off-by: default avatarGeorgi Djakov <georgi.djakov@linaro.org>
      Link: https://lkml.kernel.org/r/20191126153437.11808-1-georgi.djakov@linaro.orgTested-by: default avatarRob Clark <robdclark@gmail.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      d8a82587
    • Martin Blumenstingl's avatar
      ARM: dts: meson8: fix the size of the PMU registers · 3adc34ef
      Martin Blumenstingl authored
      commit 46c9585e upstream.
      
      The PMU registers are at least 0x18 bytes wide. Meson8b already uses a
      size of 0x18. The structure of the PMU registers on Meson8 and Meson8b
      is similar but not identical.
      
      Meson8 and Meson8b have the following registers in common (starting at
      AOBUS + 0xe0):
        #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2)
        #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2)
        #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2)
        #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2)
      
      Meson8b additionally has these three registers:
        #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2)
        #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2)
        #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2)
      
      Thus we can assume that the register size of the PMU IP blocks is
      identical on both SoCs (and Meson8 just contains some reserved registers
      in that area) because the CEC registers start right after the PMU
      (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2).
      
      The upcoming power domain driver will need to read and write the
      AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated
      size is needed for that driver to work.
      
      Fixes: 4a5a2711 ("ARM: dts: meson8: add support for booting the secondary CPU cores")
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      3adc34ef
  2. 17 Jan, 2020 32 commits