- 22 Apr, 2022 22 commits
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Arınç ÜNAL authored
pinctrl-rt2880.c and pinmux.h make up the Ralink pinctrl driver. Rename pinctrl-rt2880.c to pinctrl-ralink.c. Rename pinmux.h to pinctrl-ralink.h. Fix references to it. Rename functions that include "rt2880" to "ralink". Remove PINCTRL_RT2880 symbol and make the existing PINCTRL_RALINK symbol compile pinctrl-ralink.c. Change the bool to "Ralink pinctrl driver". Signed-off-by:
Arınç ÜNAL <arinc.unal@arinc9.com> Reviewed-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Arınç ÜNAL authored
The functions that include "MT7628(an)" are for MT7628 and MT7688 SoCs. Rename them to MT76X8 to refer to both of the SoCs. Signed-off-by:
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.19 - Add support for the new RZ/G2UL SoC, - Add drive-strength support for R-Car E3, - Add RPC/QSPI pin groups on R-Car E3 and E3, - Miscellaneous fixes and improvements.
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Srinivasa Rao Mandadapu authored
Update bulk clock voting to optional voting as ADSP bypass platform doesn't need macro and decodec clocks, as these macro and dcodec GDSC switches are maintained as power domains and operated from lpass clock drivers. Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by:
Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-8-git-send-email-quic_srivasam@quicinc.comSigned-off-by:
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Srinivasa Rao Mandadapu authored
Add pin control support for SC7280 LPASS LPI. Signed-off-by:
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Srinivasa Rao Mandadapu authored
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver to allow reusing the common code in the addition of subsequent platforms. Signed-off-by:
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Srinivasa Rao Mandadapu authored
Update custom pin group structure members with framework generic group_desc structure and replace the driver's custom pinctrl_ops with framework provided generic pin control group functions to avoid redundant code written in lpass lpi driver. Signed-off-by:
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Srinivasa Rao Mandadapu authored
Update NO_SLEW macro to LPI_NO_SLEW macro as this driver lpi specific. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1650285427-19752-4-git-send-email-quic_srivasam@quicinc.comSigned-off-by:
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Srinivasa Rao Mandadapu authored
Add device tree binding Documentation details for Qualcomm SC7280 LPASS LPI pinctrl driver. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Srinivasa Rao Mandadapu authored
Change generic lpass lpi pincotrol bindings file to SoC specific file, to distinguish and accomadate other SoC specific dt bindings. Signed-off-by:
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Sebastian Reichel authored
Add compatible string for rk3588 pin controller. No other changes are required, since the new controller can use the old binding. Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220422170920.401914-12-sebastian.reichel@collabora.comSigned-off-by:
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Linus Walleij authored
The MC2 MMC interface can be configured with the FBCLK (feedback clock) unconnected, leaving the pin available for reuse for something else. Add a group mc2_a_2 for this. Signed-off-by:
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Lv Ruyi authored
Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately.Make the code simpler without functional changes. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Lv Ruyi <lv.ruyi@zte.com.cn> Link: https://lore.kernel.org/r/20220418020238.2556989-1-lv.ruyi@zte.com.cnSigned-off-by:
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Paul Cercueil authored
By being a bit smarter about how the SoC version checks are performed, it is possible to have all the code paths that correspond to SoCs disabled in the kernel config automatically marked as dead code by the compiler, and therefore garbage-collected. With this patch, when compiling a kernel that only targets the JZ4760 for instance, the driver is now about 4.5 KiB smaller. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220412162218.32509-1-paul@crapouillou.netSigned-off-by:
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Johan Jonker authored
Add the compatible string "rockchip,rk3036-pinctrl" in already in use in rk3036.dtsi to rockchip,pinctrl.yaml. Signed-off-by:
Johan Jonker <jbx6244@gmail.com> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
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Alexander Stein authored
Convert the i.MX7D pinctrl binding to DT schema format using json-schema Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220303150653.1903910-1-alexander.stein@ew.tq-group.comSigned-off-by:
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Krzysztof Kozlowski authored
The MODULE_DEVICE_TABLE already creates proper alias for platform driver. Having another MODULE_ALIAS causes the alias to be duplicated. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407202509.23228-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Qianggui Song authored
The kernel test robot reported a warning as below: >> drivers/pinctrl/meson/pinctrl-meson-s4.c:178:27: warning: unused variable 'tdm_sclk1_c_pins' [-Wunused-const-variable] static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 }; Fix it by adding missing description about this pins Fixes: 775214d3 ("pinctrl: meson: add pinctrl driver support for Meson-S4 Soc") Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
Qianggui Song <qianggui.song@amlogic.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220330023720.18238-1-qianggui.song@amlogic.comSigned-off-by:
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Fabien Parent authored
Set the pinctrl driver as built-in by default if ARM64 and ARCH_MEDIATEK are enabled. Fixes: 6cf5e9ef ("pinctrl: add pinctrl driver on mt8195") Signed-off-by:
Fabien Parent <fparent@baylibre.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220327160813.2978637-1-fparent@baylibre.comSigned-off-by:
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Caleb Connolly authored
Add support for deferred PIN_CONFIG_INPUT_ENABLE handling. Signed-off-by:
Caleb Connolly <kc@postmarketos.org> Acked-by:
Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220328005005.72492-4-kc@postmarketos.orgSigned-off-by:
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Caleb Connolly authored
Handle the PIN_CONFIG_INPUT_ENABLE param for configuring GPIOs as input. Signed-off-by:
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Caleb Connolly authored
Add support for deferring other params like PIN_CONFIG_INPUT_ENABLE. This will be used to add support for PIN_CONFIG_INPUT_ENABLE to the driver. Fixes: e7165b1d ("pinctrl/rockchip: add a queue for deferred pin output settings on probe") Fixes: 59dd178e ("gpio/rockchip: fetch deferred output settings on probe") Signed-off-by:
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- 21 Apr, 2022 7 commits
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Michael Walle authored
The SoC supports a debug clock output of its internal clocks. Depending on the clk_sel input (GPIO_31) clk_mon (GPIO_30) will output either cpu_clk/64 or sys_clk/64. This is very useful for debugging and is missing in the pinmux table. Add it. Signed-off-by:
Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220326192848.2944519-2-michael@walle.ccSigned-off-by:
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Michael Walle authored
According to the reference manual, you can mux the PWM output on GPIO27 and GPIO51. This was missing in the pinmux table. Add it. Tested on a LAN9668 on GPIO51. Signed-off-by:
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Michael Walle authored
Convert the ocelot-pinctrl device tree binding to the new YAML format. Additionally to the original binding documentation, add interrupt properties which are optional and already used on several SoCs like SparX-5, Luton, Ocelot and LAN966x but were not documented before. Also, on the sparx5 and the lan966x SoCs there are two items for the reg property. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20220319204628.1759635-7-michael@walle.ccSigned-off-by:
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Rohit Agarwal authored
PMX65 pmic support gpio controller so add compatible. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1649048650-14059-3-git-send-email-quic_rohiagar@quicinc.comSigned-off-by:
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Rohit Agarwal authored
Add support for the PMX65 GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by:
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Stefan Wahren authored
The commit c8013355 ("ARM: dts: gpio-ranges property is now required") fixed the GPIO probing issues caused by "pinctrl: bcm2835: Change init order for gpio hogs". This changed only the kernel DTS files. Unfortunately it isn't guaranteed that these files are shipped to all users. So implement the necessary backward compatibility for BCM2835 and BCM2711 platform. Fixes: 266423e6 ("pinctrl: bcm2835: Change init order for gpio hogs") Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Tested-by:
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Stefan Wahren authored
Since commit 2ab73c6d ("gpio: Support GPIO controllers without pin-ranges") the device tree nodes of GPIO controller need the gpio-ranges property to handle gpio-hogs. Unfortunately it's impossible to guarantee that every new kernel is shipped with an updated device tree binary. In order to provide backward compatibility with those older DTB, we need a callback within of_gpiochip_add_pin_range() so the relevant platform driver can handle this case. Fixes: 2ab73c6d ("gpio: Support GPIO controllers without pin-ranges") Signed-off-by:
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- 20 Apr, 2022 9 commits
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Geert Uytterhoeven authored
The PIN_CFG_* capabilities are always listed in the order they are defined, except in the "TMS/SWDIO" pin definition. Fix the order, to increase uniformity. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f9b18be9e5402531d058bd2479b4881377f9b8b6.1649857772.git.geert+renesas@glider.be
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Geert Uytterhoeven authored
The last __init annotations were removed from these source files almost one decade ago. Signed-off-by:
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Lad Prabhakar authored
GPIO (PINCTRL) block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so instead of selecting PINCTRL_RZG2L config for each SoC select PINCTRL_RZG2L config option if ARCH_RZG2L is enabled. The ARCH_RZG2L config option is already selected by ARCH_R9A07G043, ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220406075318.14385-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Biju Das authored
RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin definitions are different compared to RZ/G2L. This patch adds a new compatible to take care of these differences by adding r9a07g043_data with r9a07g043_gpio_configs and rzg2l_dedicated_pins.common. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
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Geert Uytterhoeven authored
Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77995 PFC driver. They are to be used when a QSPI Flash, Octal-SPI Flash, or HyperFlash is connected. Signed-off-by:
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Geert Uytterhoeven authored
Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77990 PFC driver. They are to be used when an Octal-SPI Flash or HyperFlash is connected. Redefine the QSPI[01] pin groups using the RPC DQ[0:7] pin data, to save memory. Signed-off-by:
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Wolfram Sang authored
According to R-Car Gen3 HW documentation 2.20 onwards, drive-strength is introduced to r8a77990. It is also documented for r8a774c0. Add it to the pinctrl driver. Signed-off-by:
LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220320092542.2308-3-wsa+renesas@sang-engineering.comSigned-off-by:
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Wolfram Sang authored
Needed to support R-Car E3 and RZ/G2E drive regs. Signed-off-by:
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Geert Uytterhoeven authored
The checker code to iterate over all drive strength and bias register description items is cumbersome, due to the repeated calculation of indices, and the use of hardcoded array sizes. The latter was done under the assumption they would never need to be changed, which turned out to be false. Increase readability by introducing helper macros to access drive strength and bias register description items. Increase maintainability by replacing hardcoded numbers by array sizes calculated at compile-time. Signed-off-by:
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- 19 Apr, 2022 2 commits
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Nícolas F. R. A. Prado authored
Add the gpio-line-names optional property to the pinctrl-mt8192 binding to prevent dt_binding_check warnings when it is present in the pinctrl node in the Devicetree. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Acked-by:
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Nícolas F. R. A. Prado authored
Add the mediatek,pull-up-adv property to the pinctrl-mt8192 dt-binding to allow configuring pull-up resistors on the pins of MT8192. It is the same as in mt8183-pinctrl. Signed-off-by:
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