- 07 Jun, 2022 16 commits
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David Zhang authored
[why & how] Expose vendor specific DPCD registers for rate controlling the eDP sink TCON's refresh rate during PSR active. When used in combination with PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for short. v2: Add all DPCD registers required Signed-off-by:
David Zhang <dingchen.zhang@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Aric Cyr authored
This version brings along the following: - DPP DTO fix - Transient encoder fix - Restrict the reading of LTTPR capabilities in LTTPR mode - Increase maximum stages for BB - Distinguish HDMI DTO from DP DTO Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Chris Park authored
[Why] For Pixel Rate control, when on HDMI, HDMI DTO should be selected instead of DP DTO. [How] Add HDMI member to dtbclk_dto_params, so it can be used tell apart HDMI and DP DTO in the future. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Chris Park <chris.park@amd.com> Tested-by:
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Lei, Jun authored
[why] Some parts are consuming dangerously close to maximum number of states supported when updating the BB (i.e. 8). [how] Change maximum stages from 9 to 20. Reviewed-by:
Jun Lei <jun.lei@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] In some scenarios it is possible for the encoder assignment module to be set to "transient" mode even though there are no new encoder assignments. This can lead to incorrect results when querying encoder assignment, which in turn can cause incorrect displays to be manipulated. [How] Only allow encoder assignment to be in transient mode of operation when there are valid new encoder assignments. Reviewed-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
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Duncan Ma authored
[Why] When switching from 1 pipe to 4to1 mpc combine, DppDtoClk aren't enabled for the disabled pipes pior to programming the pipes. Upon optimizing bandwidth, DppDto are enabled causing intermittent underflow. [How] Update dppclk dto whenever pipe are flagged to enable. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by:
Hansen Dsouza <Hansen.Dsouza@amd.com> Acked-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
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Aric Cyr authored
This version brings along the following: - Optimized blank calculations - More robust DP MST hotplug support - eDP bug fix relating to ODM - Revert a patch that caused a regression with DP - min comp buffer size fix - Make DP easier to debug - Calculate the maximum OLED brightness correctly - 3 plane MPO. Acked-by:
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Anthony Koo authored
Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Hansen Dsouza authored
[why and how] 3 plane MPO is a new feature missing in a few resource files Enable 3 plane MPO by setting slave planes to 2 Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Roman Li authored
[Why] For OLED eDP the Display Manager uses max_cll value as a limit for brightness control. max_cll defines the content light luminance for individual pixel. Whereas max_fall defines frame-average level luminance. The user may not observe the difference in brightness in between max_fall and max_cll. That negatively impacts the user experience. [How] Use max_fall value instead of max_cll as a limit for brightness control. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Tested-by:
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Wenjing Liu authored
[why] 1. When HPD deassertion is pulled in the middle of enabe stream link training, we will abort current training and turn off PHY. This causes current link settings to be zeroed this causes later stream enablement sequence to fail as we prefer to carry on enablement process despite of link training failure for SST. 2. When HPD is toggled after detection before before the enable stream sequence as a result. There could be a race condition where we could end up enable stream based on the previous link even though the link is updated after the HPD toggle. This causes an issue where our link bandwidth is no longer enough to accommodate the timing therefore causes us to oversubscribe MST payload time slots. As discussed we decided to add basic sanity check to make sure that our code can handle the oversubscription failure silently without system hang. [how] 1. Keep PHY powered on when HPD is deasserted during enable stream and wait for the detection sequence to power it off later. 2. Do not allocate payload if the required timeslot for current timing is greater than 64 timeslots. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Duncan Ma authored
[Why] In 3-way mpo pipes, there is a case that we overbook the CRB buffer size. At rare instances, overbooking the crb will cause underflow. This only happens when det_size changes dynamically based on pipe_cnt. [How] Set min compbuff size to 1 segment when preparing BW. Reviewed-by:
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Duncan Ma authored
[Why] For panels with pixel clock > 1200MHz that require ODM in pre-OS, when driver is disabled in OS, odm is enabled. Upon driver enablement, corruption is seen if odm was originally enabled. DP_PIXEL_COMBINE and pixelclk must be programmed prior to programming the optc-odm registers. However, eDP displays aren't blanked prior to initializing odm in this case. [How] Upon driver enablement, check whether odm is enabled, if so, blank eDP prior to programming optc-odm registers. Reviewed-by:
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Jimmy Kizito authored
[Why] LTTPR capable devices on the DisplayPort path may assume that extended LTTPR AUX timeouts will be used after LTTPR capabilities are read. When DPTX operates in non-LTTPR mode, AUX timeouts are not extended and this can result in AUX transactions timing out. [How] Use shared helper function to determine LTTPR mode and do not read LTTPR capabilities in non-LTTPR mode. Reviewed-by:
Mustapha Ghaddar <Mustapha.Ghaddar@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
This reverts commit 8440f575. Causes a hang when hotplugging DP, shutting down system, or enabling dual eDP. Reviewed-by:
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Guchun Chen authored
This reverts commit b992a190. This causes regression in GPU reset related test. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: ricetons@gmail.com Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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- 06 Jun, 2022 24 commits
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Alex Deucher authored
Set the default reset method to mode2 for SMU IP v13.0.4 Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Alexey Kodanev authored
The last case label can write two buffers 'mc_reg_address[j]' and 'mc_data[j]' with 'j' offset equal to SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE since there are no checks for this value in both case labels after the last 'j++'. Instead of changing '>' to '>=' there, add the bounds check at the start of the second 'case' (the first one already has it). Also, remove redundant last checks for 'j' index bigger than array size. The expression is always false. Moreover, before or after the patch 'table->last' can be equal to SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE and it seems it can be a valid value. Detected using the static analysis tool - Svace. Fixes: 69e0b57a ("drm/radeon/kms: add dpm support for cayman (v5)") Signed-off-by:
Alexey Kodanev <aleksei.kodanev@bell-sw.com> Signed-off-by:
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Alex Deucher authored
Add proper handling for PPC64. Reviewed-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Alex Deucher authored
Fixes "no previous prototype" warnings. Reviewed-by:
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Alex Deucher authored
Add comments to clarify code that is safe, but triggers and smatch warning. Link: https://lists.freedesktop.org/archives/amd-gfx/2022-June/079905.htmlSigned-off-by:
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Wayne Lin authored
[Why] Once mst topology is constructed, later on new connected monitors are reported to source by CSN message. Within CSN, there is no carried info of DPCD_REV comparing to LINK_ADDRESS reply. As the result, we might leave some ports connected to DP but without DPCD revision number which will affect us determining the capability of the DP Rx. [How] Send out remote DPCD read when the port's dpcd_rev is 0x0 in detect_ctx(). Firstly, read out the value from DPCD 0x2200. If the return value is 0x0, it's likely the DP1.2 DP Rx then we reques revision from DPCD 0x0 again. Reviewed-by:
Hersen Wu <hersenwu@amd.com> Acked-by:
Wayne Lin <Wayne.Lin@amd.com> Tested-by:
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Gabe Teeger authored
[Why] The existing calculations in DCN3.1 were placeholder and need to be replaced with HW team approved calculations. [How] The new calculations add new parameters to the bounding box and pipe params - VblankNom and the bounding box default. The placeholder calculations are dropped from DCN3.1 in the meantime while we work out hardware approved replacements. Also fix a bug where we wipe out other register contents with a REG_SET instead of a REG_UPDATE for the register we were programming the min_dst_y_next_start_optimized. Reviewed-by:
Gabe Teeger <gabe.teeger@amd.com> Tested-by:
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Leo Li authored
[WHY] For additional power savings, PSR SU (also referred to as PSR2) can be enabled on eDP panels with PSR SU support. PSR2 saves more power compared to PSR1 by allowing more opportunities for the display hardware to be shut down. In comparison to PSR1, Shut down can now occur in-between frames, as well as in display regions where there is no visible update. In otherwords, it allows for some display hw components to be enabled only for a **selectively updated** region of the visible display. Hence PSR SU. [HOW] To define the SU region, support from the OS is required. OS needs to inform driver of damaged regions that need to be flushed to the eDP panel. Today, such support is lacking in most compositors. Therefore, an in-between solution is to implement PSR SU for MPO and cursor scenarios. The plane bounds can be used to define the damaged region to be flushed to panel. This is achieved by: * Leveraging dm_crtc_state->mpo_requested flag to identify when MPO is enabled. * If MPO is enabled, only add updated plane bounds to dirty region. Determine plane update by either: * Existence of drm damaged clips attached to the plane (added by a damage-aware compositor) * Change in fb id (flip) * Change in plane bounds (position and dimensions) * If cursor is enabled, the old_pos and new_pos of cursor plus cursor size is used as damaged regions(*). (*) Cursor updates follow a different code path through DC. PSR SU for cursor is already implemented in DC, and the only thing required to enable is to set DC_PSR_VERSION_SU_1 on the eDP link. See dcn10_dmub_update_cursor_data(). Signed-off-by: -
David Zhang authored
[why] To involve the cursor position into dirty rectangle calculation. [how] - separate plane and cursor update by different DMUB command - send the cursor information while cursor updating, when updating cursor position/attribute, store cursor pos/attr to hubp, and notify dmub FW to exit psr before program cursor registers Signed-off-by:
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David Zhang authored
[why] Currently the psr configuration parameters are hardcoded before feeding into the DC helper before passing to DMUB FW. We'd rework to call a shared helper to calculate/update generic psr config fields which are relying on the stream timing and eDP sink PSR caps to avoid hard-coding. [how] - drop part of hard-coded psr config fields by replacing w/ the call of helper from DM before feeding into DC link setup psr helper - For those DM specific psr config fields, e.g. allow smu opt, is not to be set/updated from the shared helper but to rely on the DC feature mask - for the psr version field in psr_config structure, since only the field psr_version of DC link psr_settings matters for that fed to DMUB FW, thus no need to set/update the psr_version field of psr_config structure. Signed-off-by:
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David Zhang authored
[why] Currently the amdgpu DM psr configuration parameters are hardcoded before feeding into the DC helper to setup PSR. We would define a helper which is to calculate parts of the psr config fields to avoid hard-coding. [how] To make helper shareable, declare and define the helper in the module_helper, to set/update below fields: - psr remote buffer setup time - sdp tx line number deadline - line time in us - su_y_granularity - su_granularity_required - psr_frame_capture_indication_req - psr_exit_link_training_required add another helper to check given the stream context, if there is only one stream and the output is eDP panel connected. changes in v2: ------------------ - add detailed comment for how psr setup time is calculated as per eDP 1.5 spec Cc: Chandan Vurdigerenataraj <chandan.vurdigerenataraj@amd.com> Signed-off-by:
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David Zhang authored
[why] Some specific TCON chip has HW limitation to support PSRSU+DSC. [how] Force ffu mode when DSC enabled if we detect it is the specific model from sink OUI DPCD. And disable ABM update for this case. Signed-off-by:
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David Zhang authored
[why] Feature requires synchronization of dig, pipe, and cursor locking between driver and DMUB fw for PSR-SU [how] return True if PSR-SU in the checker should_use_dmub_lock() Signed-off-by:
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David Zhang authored
[Why & How] While support ALPM, do ALPM state transition while PSR entry/exit. ALPM is needed for PSR-SU feature, and since the function is ready, we'd enable it by default. - Add psr level definition to enable/disable ALPM and set ALPM powerdone mode. - Enable ALPM by default Signed-off-by:
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David Zhang authored
[why] When DC driver send PSR exit dmub command to DMUB FW, it might not wait until PSR exit. Then it may hit the following deadlock situation. 1. DC driver send HW LOCK command to DMUB FW due to frame update 2. DMUB FW Set the HW lock 3. DMUB execute PSR exit sequence and stuck at polling DPG Pending register due to the HW Lock is set 4. DC driver ask DMUB FW to unlock HW lock, but DMUB FW is polling DPG pending register [how] The reason why DC driver doesn't wait until PSR exit is because some of the PSR state machine state is not update the dc driver. So when DC driver read back the PSR state, it take the state for PSR inactive. Signed-off-by:
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David Zhang authored
[why] The current PSR SU programming margin is fixed base on FHD 60HZ panel. If the resolution and refresh rate become higher, the time of current margin might not cover the programming SU time. [how] Notice that the programming SU time is the same among different panels. Instead of fixing the margin with target line number, change the margin unit to micro second which indicate the time needed for programming SU. Then FW set the margin line number base on the line time and margin time. Signed-off-by:
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David Zhang authored
[Why & how] We only support line capture indication as 0 for PSRSU Signed-off-by:
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David Zhang authored
[Why] The Y-granularity panel parameter indicate the grid pattern granularity in the Y direction for PSRSU. [How] Send the Y-granularity data by PSR_COPY_SETTINGS dmub command. Signed-off-by:
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Arunpravin Paneer Selvam authored
Enable pipe1 support starting from SIENNA CICHLID asic Signed-off-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Arunpravin Paneer Selvam authored
Starting from SIENNA CICHLID asic supports two gfx pipes, enabling two graphics queues, 1 on each pipe, pipe0 queue0 would be the normal piority queue and pipe1 queue0 would be the high priority queue Only one queue per pipe is visble to SPI, SPI looks at the priority value assigned to CP_GFX_HQD_QUEUE_PRIORITY from each of the queue's HQD/MQD. Create contexts applying AMDGPU_CTX_PRIORITY_HIGH which submits job to the high priority queue on GFX pipe1. There would be starvation of LP workload if HP workload is always available. v2: - remove unnecessary check(Nirmoy) - make pipe1 hardware support a separate patch(Nirmoy) - remove duplicate code(Shashank) - add CSA support for second gfx pipe(Alex) v3(Christian): - fix incorrect indentation - merge COMPUTE and GFX switch cases as both calls the same function. v4: - rebase w/ latest code base Signed-off-by:
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Somalapuram Amaranath authored
Added device coredump information: - Kernel version - Module - Time - VRAM status - Guilty process name and PID - GPU register dumps v1 -> v2: Variable name change v1 -> v2: NULL check v1 -> v2: Code alignment v1 -> v2: Adding dummy amdgpu_devcoredump_free v1 -> v2: memset reset_task_info to zero v2 -> v3: add CONFIG_DEV_COREDUMP for variables v2 -> v3: remove NULL check on amdgpu_devcoredump_read Signed-off-by:
Somalapuram Amaranath <Amaranath.Somalapuram@amd.com> Reviewed-by:
Shashank Sharma <Shashank.sharma@amd.com> Signed-off-by:
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Somalapuram Amaranath authored
Allocate memory for register value and use the same values for devcoredump. v1 -> v2: Change krealloc_array() to kmalloc_array() v2 -> v3: Fix alignment Signed-off-by:
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David Zhang authored
[Why] To support PSR2 Source DPCD configuration [How] Update the PSR2 Source DPCD settings while the PSR2 enabled Signed-off-by:
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David Zhang authored
[why & how] We need to implement the VSC packet rev4 that is required by PSRSU. Follow the eDP 1.5 spec pg. 257 changes in v2: ------------------- - set vsc packet rev2 for PSR1 Cc: Chandan Vurdigerenataraj <chandan.vurdigerenataraj@amd.com> Signed-off-by:
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