- 04 Oct, 2021 40 commits
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Alex Deucher authored
Handle SRIOV requirements when adding IP blocks. v2: add comment about UVD/VCE support on vega20 SR-IOV Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Split into several smaller per IP functions to make it easier to handle ordering issues for things like SR-IOV in a follow up patch. Acked-by:
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Alex Deucher authored
Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by:
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Alex Deucher authored
For new chips with no explicit entry in the PCI ID list. Reviewed-by:
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Alex Deucher authored
Add a new asic type for asics where we don't have an explicit entry in the PCI ID list. We don't need an asic type for these asics, other than something higher than the existing ones, so just use this for all new asics. Reviewed-by:
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Alex Deucher authored
Default to PSP ucode loading unless the user specifies direct. Acked-by:
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Alex Deucher authored
Use the table rather than asic specific harvest registers. v2: remove harvesting register checking Signed-off-by: -
Alex Deucher authored
Handled by IP discovery now. Acked-by:
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Alex Deucher authored
Handled by IP discovery now. Acked-by:
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Alex Deucher authored
Rather than hardcoding it. We already have the number of VCN instances from a previous patch, so just update the VCN instances for chips with static tables. v2: squash in checks for SDMA3,4 (Guchun) v3: clarify VCN changes Reviewed-by:
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Guchun Chen authored
They are missed. Acked-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Alex Deucher authored
So we can store the VCN IP revision for each instance of VCN. Acked-by:
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Guchun Chen authored
Otherwise, we will run into error case path. v2: fix build when CONFIG_DRM_AMD_DC_DCN is not set Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: squash in fix for navy flounder and sienna cichlid Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: switch if statement to a switch statement Acked-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by: -
Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
We are not going to support any new chips with the old non-DC code so make it the default. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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Alex Deucher authored
Rather than hardcoding based on asic_type, use the IP discovery table to configure the driver. Reviewed-by:
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Alex Deucher authored
for consistency with other SoCs. Acked-by:
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Alex Deucher authored
Hardcode the IP versions for asics without IP discovery tables and then enumerate the asics based on the IP versions. TODO: fix SR-IOV support v2: Squash in HDP fix for Renoir Acked-by:
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Alex Deucher authored
So they can be driven by IP discovery table. Acked-by:
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Alex Deucher authored
So we can track grab the appropriate DCE info out of the IP discovery table. This is a separare IP from DCN. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: drop unrelated change Acked-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by: -
Alex Deucher authored
Rather than hardcoding based on asic_type, use the IP discovery table to configure the driver. v2: rebase Reviewed-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: rebase Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: rebase v3: switch some if statements to switch statements v4: add yellow carp fix (Yifan) v5: squash in fixes for YC and GS (Alex) Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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