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- 30 Dec, 2021 1 commit
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Wenjing Liu authored
[why] When there are more DP2.0 RXs connected than the number HPO DP link encoders we have, we need to dynamically allocate HPO DP link encoder to the port that needs it. [how] Only allocate HPO DP link encoder when it is needed. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 01 Dec, 2021 1 commit
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Meenakshikumar Somasundaram authored
[Why] During otg sync trigger, plane states are used to decide whether the otg is already synchronized or not. There are scenarions when otgs are disabled without plane state getting disabled and in such case the otg is excluded from synchronization. [How] Introduced pipe_idx_syncd in pipe_ctx that tracks each otgs master pipe. When a otg is disabled/enabled, pipe_idx_syncd is reset to itself. On sync trigger, pipe_idx_syncd is checked to decide whether a otg is already synchronized and the otg is further included or excluded from synchronization. Reviewed-by:
Mustapha Ghaddar <mustapha.ghaddar@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
meenakshikumar somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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- 06 Oct, 2021 1 commit
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Jimmy Kizito authored
[Why & How] USB4 endpoints are dynamically mapped. We create additional link encoders for USB4 use when DC is created and destroy them when DC is destructed Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by:
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- 01 Sep, 2021 3 commits
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Fangzhi Zuo authored
1. Retrieve 128/132b link cap. 2. 128/132b link training and payload allocation. 3. UHBR10 link rate support. [squash in warning fixes - Alex] Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Fangzhi Zuo authored
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | | v v v | +---------------------+ | | HPO Stream Encoder | | +---------------------+ | | | v | +--------------------+ | | HPO Link Encoder | v +--------------------+ [squash in warning fixes - Alex] Signed-off-by: -
Fangzhi Zuo authored
HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | v v v v +----------------------+ | HPO Stream Encoder | +----------------------+ [squash in warning fixes - Alex] Signed-off-by:
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- 02 Mar, 2021 1 commit
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Jimmy Kizito authored
[Why] Currently the creation of link encoder objects is tightly coupled to the creation of link objects. Decoupling link encoder object creation is a preliminary step in the process of allowing link encoders to be dynamically assigned to links. [How] Add "minimal" link encoder objects which are not associated with any link until required. Tested-by:
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- 22 Feb, 2021 1 commit
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Vladimir Stempen authored
[why] Vendor based fan noise improvement [how] Report timing synchronizable when DP streams time frame difference is less than 0.05 percent. Adjust DP DTOs and sync displays using MASTER_UPDATE_LOCK_DB_X_Y Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Acked-by:
Bindu Ramamurthy <bindu.r@amd.com> Tested-by:
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- 04 Nov, 2020 1 commit
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Alex Deucher authored
Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1) Signed-off-by:
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- 01 Jul, 2020 1 commit
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Bhawanpreet Lakha authored
Add support for managing resources for DCN3 Signed-off-by:
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- 21 May, 2020 1 commit
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Dmytro Laktyushkin authored
Current odm/mpc combine logic to detect which pipes need to split logically is flawed leading to incorrect pipe merge/split operations being taken. This change cleans up the logic and fixes the logical errors. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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- 05 May, 2020 1 commit
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Aric Cyr authored
[Why] What a mode change is requested for the same timing a full stream reset can occur in some cases which causes monitor to blank for a few seconds. [How] Do not consider infoframe updates as needing a full stream reset as they will be handled on the first flip after a modeset when surface information is available. Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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- 12 Feb, 2020 1 commit
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Alex Deucher authored
It's used by more than just DCN2.0. Fixes missing symbol when amdgpu is built without DCN support. Reviewed-by:
Zhan Liu <zhan.liu@amd.com> Tested-by:
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- 18 Dec, 2019 1 commit
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Charlene Liu authored
Add HDMI 2.x audio bandwidth check Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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- 13 Nov, 2019 1 commit
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Bhawanpreet Lakha authored
[Why] DCN2 and DSC are stable enough to be build by default. So drop the flags. [How] Remove them using the unifdef tool. The following commands were executed in sequence: $ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' In addition: * Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup NV defninitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN2 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * dce/dce_dmcu.c: dcn20_*lock_phy() * dce/dce_dmcu.c: dcn20_funcs * dce/dce_dmcu.c: dcn20_dmcu_create() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init() Signed-off-by:Leo Li <sunpeng.li@amd.com> Signed-off-by:
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- 17 Sep, 2019 1 commit
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Charlene Liu authored
[Description] 1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update) 2. using memory type to convert UMC's MCLK to Yclk. Signed-off-by:
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- 13 Sep, 2019 1 commit
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Charlene Liu authored
[Description] 1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update) 2. using memory type to convert UMC's MCLK to Yclk. Signed-off-by:
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- 23 Aug, 2019 1 commit
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Dmytro Laktyushkin authored
Currently odm is handled using top_bottom pipe by special casing the differing opps to differentiate from mpc combine. Since top/bottom pipe list was made to track mpc muxing this creates difficulties in adding a 4 pipe odm case support. Rather than continue using mpc combine list, this change reworks odm to use it's own linked list to keep track of odm combine pipes. This also opens up options for using mpo with odm, if a practical use case is ever found. Signed-off-by:
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- 22 Jun, 2019 1 commit
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Harry Wentland authored
Add support for DCN2 DSC (Display Stream Compression) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ +-------+ | | OPP | <--> | DSC | | +-------+ +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ v2: rebase (Alex) Signed-off-by:
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- 21 Jun, 2019 1 commit
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Harry Wentland authored
Add DCN2 resource definition and HW Sequencer changes. Signed-off-by:
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- 31 May, 2019 1 commit
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Eric Yang authored
[Why] First step of refactoring clk mgr to better handle different ways of handling clock operations. Clock operation policies are soc specific and not just DCN vesion specific. It is not a hw resource, should not be in the resource pool. [How] Change clock manager creation to be based on HW internal ID, rename clock manager members to be more clear. Move clock manager out of resource. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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- 28 Mar, 2019 3 commits
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Dmytro Laktyushkin authored
Currently only top pipe gets output tf programmed. This change makes all odm head pipes get output tf programmed. Signed-off-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Harry Wentland authored
[WHY] The resource constructor currently needs num_virtual_links from init_data but will need access to other items provided by DM. [HOW] Pass init_data into DCN create_resource_pool functions. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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Jun Lei authored
[why] existing logic finds "first free pipe from 5 -> 0" to split this will cause certain sequences to require DC to move an MPCC from one tree to another, which is unsupported this leads to blackscreen to mitigate this problem, we will always try to acquire the "preferred" pipe, and each pipe has a unique preferred pipe this means we avoid most of the scenarios where pipe splitting leads to moving MPCC from one tree to another Signed-off-by:
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- 21 Mar, 2019 1 commit
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Dmytro Laktyushkin authored
There are issues removing surfaces/streams when odm is active. This is a step to fix that Signed-off-by:
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- 05 Nov, 2018 1 commit
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Dmytro Laktyushkin authored
This is done to clear up the clock programming sequence since the only time we need to notify pplib is after clock update. This also renames the clk block to dccg, at the moment this block contains both clock management and dccg functionality. Signed-off-by:
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- 09 Oct, 2018 1 commit
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Su Sung Chung authored
[Why] Previously bandwidth validation was failing because swizzle mode was not initialized during plane_state allocation. The swizzle mode was calculated using pixed format which is how swizzle mode is initially calculated in addrlib. [How] * Set default swizzle mode for validation to DC_SW_UNKNOWN * Created new function in dcn10_assign_swizzle_mode which sets the plane swizzle mode based on selected pixed format * Added the call of assign_swizzle_mode into dc_validate_global_state * Set failsafe swizzle mode back to DC_SW_LINEAR Signed-off-by:
Su Sung Chung <Su.Chung@amd.com> Reviewed-by:
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- 11 Sep, 2018 1 commit
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Hersen Wu authored
[why] AMD Stoney reference board, there are only 2 pipes (not include underlay), and 3 connectors. resource creation, only 2 I2C/AUX engines are created. Within dc_link_aux_transfer, when pin_data_en =2, refer to enengines[ddc_pin->pin_data->en] = NULL. NULL point is referred later causing system crash. [how] each asic design has fixed number of ddc engines at hw side. for each ddc engine, create its i2x/aux engine at sw side. Signed-off-by:
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- 13 Aug, 2018 1 commit
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Mikita Lipski authored
[why] We are disabling clock source while other pipes are still using it, because we don't verify the number of pipes that share it. [how] - Adding a function in resources to return the number of pipes sharing the clock source. - Checking that no one is sharing the clock source before disabling Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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- 15 Jun, 2018 1 commit
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Eric Bernstein authored
Number of OPPs to be instantiated is based on number of timing generators, not number of pipes. Signed-off-by:
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- 11 Apr, 2018 1 commit
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Julian Parkin authored
Block FP16 scaling in validate_resources codepath. Signed-off-by:
Julian Parkin <jparkin@amd.com> Reviewed-by:
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- 21 Oct, 2017 1 commit
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Charlene Liu authored
Signed-off-by:
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- 26 Sep, 2017 8 commits
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Harry Wentland authored
This simplifies clock source reprogramming a bit. Signed-off-by:
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Harry Wentland authored
Powering down the clock source during unref is unsafe as we might want to unref during atomic_check Signed-off-by:
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Jerry Zuo authored
Rename all the dc validate_context to dc_state and dc current_context to current_state. Signed-off-by:
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Andrey Grodzovsky authored
Until now new context would start as empty, then populated with exsisting pipes + new. Now we start with duplication of existing context and then add/delete from the context pipes as needed. This allows to do a per stream resource population, start discarding dc_validation_set and by this brings DC closer to to DRM. v2: Add some fixes and rebase. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
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Tony Cheng authored
new per SoC interface instead legacy interface with lots of un-used field that only cause confusion model pp_smu like one of our HW objects with func_ptr interface to call into it. struct pp_smu as handle to call pp/smu Signed-off-by:
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Bhawanpreet Lakha authored
-Flattening core_dc to dc Signed-off-by:
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Harry Wentland authored
Signed-off-by:
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Harry Wentland authored
find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream/struct dc_stream_state/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream_state_update/struct dc_stream_update/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream_state_status/struct dc_stream_status/g' Plus some manual changes Signed-off-by:
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