- 12 Jul, 2008 1 commit
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Andre Schwarz authored
On MPC5200 the PCI target control register (PCITCR) @ MBAR + 0xD6C is initialized with only bit 7 (Latrule disable) set. The 8-Bit write combine timer (Bits 24..31) should be also set to a reasonable value _greater zero_ (0x08 = default) since setting it to 0x00 leads to _very poor_ performance as a PCI target since external burst won't be possible at all. Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance. Signed-off-by:
Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by:
Grant Likely <grant.likely@secretlab.ca>
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- 03 Jul, 2008 11 commits
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Nathan Fontenot authored
Update the association of a memory section with a numa node that occurs during hotplug add of a memory section. This adds a check in the hot_add_scn_to_nid() routine for the ibm,dynamic-reconfiguration-memory node in the device tree. If present the new hot_add_drconf_scn_to_nid() routine is invoked, which can properly parse the ibm,dynamic-reconfiguration-memory node of the device tree and make the proper numa node associations. This also introduces the valid_hot_add_scn() routine as a helper function for code that is common to the hot_add_scn_to_nid() and hot_add_drconf_scn_to_nid() routines. Signed-off-by:
Nathan Fontenot <nfont@austin.ibm.com> Signed-off-by:
Paul Mackerras <paulus@samba.org>
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Nathan Fontenot authored
This splits off several pieces of code that parse the ibm,dynamic-reconfiguration-memory node of the device tree into separate helper routines. This is in preparation for the next commit that will use these helper routines. There are no functional changes in this patch. Signed-off-by:
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Nathan Fontenot authored
This updates the device tree manipulation routines so that memory add/remove of lmbs represented under the ibm,dynamic-reconfiguration-memory node of the device tree invokes the hotplug notifier chain. This change is needed because of the change in the way memory is represented under the ibm,dynamic-reconfiguration-memory node. All lmbs are described in the ibm,dynamic-memory property instead of having a separate node for each lmb as in previous device tree layouts. This requires the update_node() routine to check for updates to the ibm,dynamic-memory property and invoke the hotplug notifier chain. This also updates the pseries hotplug notifier to be able to gather information for lmbs represented under the ibm,dynamic-reconfiguration-memory node and have the lmbs added/removed. Signed-off-by:
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Nathan Fontenot authored
Use the base address of the lmb to derive the starting page frame number instead of trying to extract it from the drc index of the lmb. The drc index should not be used for this as it will, and did, break. Until this point, systems that have had memory represented in the device tree with a node for each lmb the drc index would (luckily) closely track the base address of the lmb. For example a lmb with a drc index of 8000000a would have a base address of a0000000. This correlation allowed the current code to derive the starting page frame number from the drc inddex Device tree layouts where lmbs are represented under the ibm,dynamic-reconfiguration-memory node in the ibm,dynamic-memory property do not have this correlation between the drc index and base address of the lmb. Signed-off-by:
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Nathan Fontenot authored
Allow the phandle passed to the /proc/ppc64/ofdt file to be specified in formats other than decimal. This allows us to easily specify phandle values in hex that would otherwise appear as negative integers. This is an issue on systems where the value of /proc/device-tree/ibm,dynamic-reconfiguration-memory.ibm,phandle is fffffff9. Having to pass this to the ofdt file as a string results in a large negative number, and simple_strtoul() does not handle negative numbers. Signed-off-by:
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Michael Neuling authored
Since Roland's ptrace cleanup starting with commit f65255e8 ("[POWERPC] Use user_regset accessors for FP regs"), the dump_task_* functions are no longer being used. Signed-off-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
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Michael Neuling authored
This merges and cleans up some of the ugly copy/to from user code which is required for the new fpr and vsx layout in the thread_struct. Also fixes some hard coded buffer sizes and removes a redundant fpr_flush_to_thread. Signed-off-by:
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Kumar Gala authored
To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up the code. We default to 'sync' since that is always safe and if the cpu is capable we will replace 'sync' with 'lwsync'. We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is needed. This flag could be moved elsewhere since we dont really use it for the normal CPU_FTR purpose. Finally we only store the relative offset in the fixup section to keep it as small as possible rather than using a full fixup_entry. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
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Kumar Gala authored
We need to use PPC_LCMPI otherwise we get compile errors like: arch/powerpc/lib/feature-fixups-test.S: Assembler messages: arch/powerpc/lib/feature-fixups-test.S:142: Error: Unrecognized opcode: `cmpdi' arch/powerpc/lib/feature-fixups-test.S:149: Error: Unrecognized opcode: `cmpdi' arch/powerpc/lib/feature-fixups-test.S:164: Error: Unrecognized opcode: `cmpdi' Signed-off-by:
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Michael Neuling authored
Currently we get this warning: arch/powerpc/kernel/init_task.c:33: warning: missing braces around initializer arch/powerpc/kernel/init_task.c:33: warning: (near initialization for 'init_task.thread.fpr[0]') This fixes it. Noticed by Stephen Rothwell. Signed-off-by:
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Tony Breeds authored
Currently the kernel fails to build with the above config options with: CC arch/powerpc/mm/mem.o arch/powerpc/mm/mem.c: In function 'arch_add_memory': arch/powerpc/mm/mem.c:130: error: implicit declaration of function 'create_section_mapping' This explicitly includes asm/sparsemem.h in arch/powerpc/mm/mem.c and moves the guards in include/asm-powerpc/sparsemem.h to protect the SPARSEMEM specific portions only. Signed-off-by:
Tony Breeds <tony@bakeyournoodle.com> Signed-off-by:
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- 01 Jul, 2008 28 commits
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Michael Neuling authored
This correctly hooks the VSX dump into Roland McGrath core file infrastructure. It adds the VSX dump information as an additional elf note in the core file (after talking more to the tool chain/gdb guys). This also ensures the formats are consistent between signals, ptrace and core files. Signed-off-by:
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Michael Neuling authored
Fix compile error when CONFIG_VSX is enabled. arch/powerpc/kernel/signal_64.c: In function 'restore_sigcontext': arch/powerpc/kernel/signal_64.c:241: error: 'i' undeclared (first use in this function) Signed-off-by:
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Eric B Munson authored
Currently when a 32 bit process is exec'd on a powerpc 64 bit host the value in the top three bytes of the personality is clobbered. patch adds a check in the SET_PERSONALITY macro that will carry all the values in the top three bytes across the exec. These three bytes currently carry flags to disable address randomisation, limit the address space, force zeroing of an mmapped page, etc. Should an application set any of these bits they will be maintained and honoured on homogeneous environment but discarded and ignored on a heterogeneous environment. So if an application requires all mmapped pages to be initialised to zero and a wrapper is used to setup the personality and exec the target, these flags will remain set on an all 32 or all 64 bit envrionment, but they will be lost in the exec on a mixed 32/64 bit environment. Losing these bits means that the same application would behave differently in different environments. Tested on a POWER5+ machine with 64bit kernel and a mixed 64/32 bit user space. Signed-off-by:
Eric B Munson <ebmunson@us.ibm.com> Signed-off-by:
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Bart Van Assche authored
When compiling kernel modules for ppc that include <linux/spinlock.h>, gcc prints a warning message every time it encounters a function declaration where the inline keyword appears after the return type. This makes sure that the order of the inline keyword and the return type is as gcc expects it. Additionally, the __inline__ keyword is replaced by inline, as checkpatch expects. Signed-off-by:
Bart Van Assche <bart.vanassche@gmail.com> Signed-off-by:
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Stephen Rothwell authored
Gcc 4.3 produced this warning: arch/powerpc/kernel/signal_64.c: In function 'restore_sigcontext': arch/powerpc/kernel/signal_64.c:161: warning: array subscript is above array bounds This is caused by us copying to aliases of elements of the pt_regs structure. Make those explicit. This adds one extra __get_user and unrolls a loop. Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Bernhard Walle authored
This removes the experimental status of kdump on PPC64. kdump is on PPC64 now since more than one year and it has proven to be stable. Signed-off-by:
Bernhard Walle <bwalle@suse.de> Signed-off-by:
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Andy Whitcroft authored
The implementation of huge_ptep_set_wrprotect() directly calls ptep_set_wrprotect() to mark a hugepte write protected. However this call is not appropriate on ppc64 kernels as this is a small page only implementation. This can lead to the hash not being flushed correctly when a mapping is being converted to COW, allowing processes to continue using the original copy. Currently huge_ptep_set_wrprotect() unconditionally calls ptep_set_wrprotect(). This is fine on ppc32 kernels as this call is generic. On 64 bit this is implemented as: pte_update(mm, addr, ptep, _PAGE_RW, 0); On ppc64 this last parameter is the page size and is passed directly on to hpte_need_flush(): hpte_need_flush(mm, addr, ptep, old, huge); And this directly affects the page size we pass to flush_hash_page(): flush_hash_page(vaddr, rpte, psize, ssize, 0); As this changes the way the hash is calculated we will flush the wrong pages, potentially leaving live hashes to the original page. Move the definition of huge_ptep_set_wrprotect() to the 32/64 bit specific headers. Signed-off-by:
Andy Whitcroft <apw@shadowen.org> Acked-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Andrew Lewis authored
On PowerPC processors with non-coherent cache architectures the DMA subsystem calls invalidate_dcache_range() before performing a DMA read operation. If the address and length of the DMA buffer are not aligned to a cache-line boundary this can result in memory outside of the DMA buffer being invalidated in the cache. If this memory has an uncommitted store then the data will be lost and a subsequent read of that address will result in an old value being returned from main memory. Only when the DMA buffer starts on a cache-line boundary and is an exact mutiple of the cache-line size can invalidate_dcache_range() be called, otherwise flush_dcache_range() must be called. flush_dcache_range() will first flush uncommitted writes, and then invalidate the cache. Signed-off-by: Andrew Lewis <andrew-lewis at netspace.net.au> Signed-off-by: -
Kumar Gala authored
Since most bootloaders or wrappers tend to update or add some information to the .dtb they a handled they need some working space to do that in. By default add 1K of padding via a default setting of DTS_FLAGS. Signed-off-by:
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Michael Neuling authored
Add CONFIG_VSX config build option. Must compile with POWER4, FPU and ALTIVEC. Signed-off-by:
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Michael Neuling authored
This patch extends the floating point save and restore code to use the VSX load/stores when VSX is available. This will make FP context save/restore marginally slower on FP only code, when VSX is available, as it has to load/store 128bits rather than just 64bits. Mixing FP, VMX and VSX code will get constant architected state. The signals interface is extended to enable access to VSR 0-31 doubleword 1 after discussions with tool chain maintainers. Backward compatibility is maintained. The ptrace interface is also extended to allow access to VSR 0-31 full registers. Signed-off-by:
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Michael Neuling authored
This adds the macros for the VSX load/store instruction as most binutils are not going to support this for a while. Also add VSX register save/restore macros and vsr[0-63] register definitions. Signed-off-by:
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Michael Neuling authored
Add a VSX CPU feature. Also add code to detect if VSX is available from the device tree. Signed-off-by:
Joel Schopp <jschopp@austin.ibm.com> Signed-off-by:
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Michael Neuling authored
The layout of the new VSR registers and how they overlap on top of the legacy FPR and VR registers is: VSR doubleword 0 VSR doubleword 1 ---------------------------------------------------------------- VSR[0] | FPR[0] | | ---------------------------------------------------------------- VSR[1] | FPR[1] | | ---------------------------------------------------------------- | ... | | | ... | | ---------------------------------------------------------------- VSR[30] | FPR[30] | | ---------------------------------------------------------------- VSR[31] | FPR[31] | | ---------------------------------------------------------------- VSR[32] | VR[0] | ---------------------------------------------------------------- VSR[33] | VR[1] | ---------------------------------------------------------------- | ... | | ... | ---------------------------------------------------------------- VSR[62] | VR[30] | ---------------------------------------------------------------- VSR[63] | VR[31] | ---------------------------------------------------------------- VSX has 64 128bit registers. The first 32 regs overlap with the FP registers and hence extend them with and additional 64 bits. The second 32 regs overlap with the VMX registers. This commit introduces the thread_struct changes required to reflect this register layout. Ptrace and signals code is updated so that the floating point registers are correctly accessed from the thread_struct when CONFIG_VSX is enabled. Signed-off-by: -
Michael Neuling authored
Make load_up_fpu and load_up_altivec callable so they can be reused by the VSX code. Signed-off-by:
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Michael Neuling authored
Move the altivec_unavailable code, to make room at 0xf40 where the vsx_unavailable exception will be. Signed-off-by:
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Michael Neuling authored
We are going to change where the floating point registers are stored in the thread_struct, so in preparation add some macros to access the floating point registers. Update all code to use these new macros. Signed-off-by:
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Michael Neuling authored
If we set the SPE MSR bit in save_user_regs we can blow away the VEC bit. This doesn't matter in reality as they are in fact the same bit but looks bad. Also, when we add VSX in a later patch, we need to be able to set two separate MSR bits here. Signed-off-by:
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Tony Breeds authored
Currently we set the start of the .text section to be 4Mb for pSeries. In situations where the zImage is > 8Mb we'll fail to boot (due to overlapping with OF). Move .text in a zImage from 4MB to 64MB (well past OF). We still will not be able to load large zImage unless we also move OF, to that end, add a note to the zImage ELF to move OF to 32Mb. If this is the very first kernel booted then we'll need to move OF manually by setting real-base. Signed-off-by:
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Michael Ellerman authored
Use an alternative feature section in _switch. There are three cases handled here, either we don't have an SLB, in which case we jump over the entire code section, or if we do we either do or don't have 1TB segments. Boot tested on Power3, Power5 and Power5+. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
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Michael Ellerman authored
This commit adds tests of the feature fixup code, they are run during boot if CONFIG_FTR_FIXUP_SELFTEST=y. Some of the tests manually invoke the patching routines to check their behaviour, and others use the macros and so are patched during the normal patching done during boot. Because we have two sets of macros with different names, we use a macro to generate the test of the macros, very niiiice. Signed-off-by:
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Michael Ellerman authored
This commit adds the logic to patch alternative sections. This is fairly straightforward, except for branches. Relative branches that jump from inside the else section to outside of it need to be translated as they're moved, otherwise they will jump to the wrong location. Signed-off-by:
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Michael Ellerman authored
The current feature section logic only supports nop'ing out code, this means if you want to choose at runtime between instruction sequences, one or both cases will have to execute the nop'ed out contents of the other section, eg: BEGIN_FTR_SECTION or 1,1,1 END_FTR_SECTION_IFSET(FOO) BEGIN_FTR_SECTION or 2,2,2 END_FTR_SECTION_IFCLR(FOO) and the resulting code will be either, or 1,1,1 nop or, nop or 2,2,2 For small code segments this is fine, but for larger code blocks and in performance criticial code segments, it would be nice to avoid the nops. This commit starts to implement logic to allow the following: BEGIN_FTR_SECTION or 1,1,1 FTR_SECTION_ELSE or 2,2,2 ALT_FTR_SECTION_END_IFSET(FOO) and the resulting code will be: or 1,1,1 or, or 2,2,2 We achieve this by extending the existing FTR macros. The current feature section semantic just becomes a special case, ie. if the else case is empty we nop out the default case. The key limitation is that the size of the else case must be less than or equal to the size of the default case. If the else case is smaller the remainder of the section is nop'ed. We let the linker put the else case code in with the rest of the text, so that relative branches from the else case are more likley to link, this has the disadvantage that we can't free the unused else cases. This commit introduces the required macro and linker script changes, but does not enable the patching of the alternative sections. We also need to update two hand-made section entries in reg.h and timex.h Signed-off-by:
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Michael Ellerman authored
Currently we have three versions of MAKE_FTR_SECTION_ENTRY(), the macro that generates a feature section entry. There is 64bit version, a 32bit version and version for 32bit code built with a 64bit kernel. Rather than triplicating (?) the MAKE_FTR_SECTION_ENTRY() logic, we can move the 64bit/32bit differences into separate macros, and then only have one version of MAKE_FTR_SECTION_ENTRY(). Signed-off-by:
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Michael Ellerman authored
The CPU and firmware feature fixup macros are currently spread across three files, firmware.h, cputable.h and asm-compat.h. Consolidate them into their own file, feature-fixups.h Signed-off-by:
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Michael Ellerman authored
The logic to patch CPU feature sections lives in cputable.c, but these days it's used for CPU features as well as firmware features. Move it into it's own file for neatness and as preparation for some additions. While we're moving the code, we pull the loop body logic into a separate routine, and remove a comment which doesn't apply anymore. Signed-off-by:
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Michael Ellerman authored
A bunch of code has hard-coded the value for a "nop" instruction, it would be nice to have a #define for it. Signed-off-by:
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Michael Ellerman authored
Add tests of the existing code patching routines, as well as the new routines added in the last commit. The self-tests are run late in boot when CONFIG_CODE_PATCHING_SELFTEST=y, which depends on DEBUG_KERNEL=y. Signed-off-by:
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