- 18 May, 2018 26 commits
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Alex Deucher authored
Current multi-UVD hardware uses a single clock and power source so handle all instances in the idle handler. Reviewed-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nayan Deshmukh authored
That got missed while moving the files outside of amdgpu. Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by:
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Tom St Denis authored
NFC just comments. (v2): Updated based on feedback from Alex Deucher. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Dan Carpenter authored
We added some more lines of code to this if statement but forgot to add curly braces. Fixes: 0c24e7ef ("drm/amd/powerplay: add specific changes for VEGAM in smu7_hwmgr.c") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Alex Deucher authored
- Remove unused ASICREV_IS_VEGA12_p() macro - Fix ASICREV_IS_VEGA12_P() macro to properly check against vega20 Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
Leftover from bringup. No need to keep it around for upstream. Reviewed-by:
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Alex Deucher authored
Leftover from bringup. No need to keep it around for upstream. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
This spinlock is superfluous, any call to drm_sched_entity_push_job should already be under a lock together with matching drm_sched_job_init to match the order of insertion into queue with job's fence seqence number. v2: Improve patch description. Add functions documentation describing the locking considerations Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Christian König authored
This lock isn't used any more. Signed-off-by:
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Rex Zhu authored
Screen flickering observed while running 1080p video using MPV_VAAPI/VDPAU with 4x4K@60 monitors Need to set higher mclk in this configuration. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Following change 75fbed20 we never initialize or use the GPU scheduler for KIQ and hence we need to skip KIQ ring when iterating amdgpu_ctx's scheduler entites. Signed-off-by:
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Alex Deucher authored
Must set amdgpu.exp_hw_support=1 on the kernel command line in grub to enable support. Reviewed-by:
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Feifei Xu authored
Acked-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Feifei Xu authored
v2: fix whitespace (Alex) Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Feifei Xu authored
New df helpers for 3.6. v2: switch to using df 3.6 headers (Alex) Acked-by:
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Alex Deucher authored
Needed for vega20. Acked-by:
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James Zhu authored
Vega20 ucode load type is set to AMDGPU_FW_LOAD_DIRECT for default. So UVD/VCE needn't PSP IP block up. UVD/VCE for Vega20 can be enabled at this moment. Signed-off-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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James Zhu authored
Enable 2nd instance uvd queue maping for uvd 7.2. For user, only one UVD instance presents. there is two rings for uvd decode, and 4 rings for uvd encode. Signed-off-by:
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James Zhu authored
For Vega20, the 2nd instance uvd IRQ using different client id. Enable the 2nd instance IRQ for uvd 7.2 Signed-off-by:
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James Zhu authored
For Vega20, there are two UVD hardware. Need add the 2nd IH client ID for the 2nd UVD Hardware. Signed-off-by:
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James Zhu authored
For Vega20, set num of uvd instance to 2, to enble 2nd instance. The IB test build-in registers need update for vega20 2nd instance. Signed-off-by:
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James Zhu authored
For Vega20, there are two UVD Hardware. One more UVD hardware adds one decode ring and two encode rings. So AMDGPU_MAX_RINGS need increase by 3. Signed-off-by:
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James Zhu authored
Vega20 has dual-UVD. Need add multiple instances support for uvd. Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst->. Repurpose amdgpu_ring::me for instance index, and initialize to 0. There are no any logical changes here. Signed-off-by:
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James Zhu authored
Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support multiple uvds. There are no any logical changes here. Signed-off-by:
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Feifei Xu authored
Please enable above ips on soc15.c when they're available. Reviewed-by:
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Evan Quan authored
v2: remove duplicate flag. Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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- 17 May, 2018 14 commits
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Feifei Xu authored
Please revert this patch when psp load fw is enabled. Acked-by:
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Alex Deucher authored
Use the vbios table rather than gpu info firmware. Squash of the following patches: drm/amdgpu/vg20: fallback to vbios table if gpu info fw is not available (v2) drm/amdgpu: drop gpu_info firmware for vega20 Reviewed-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang> Signed-off-by:
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Alex Deucher authored
Add support for the gfx_info table on boards that use atomfirmware. Acked-by:
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Alex Deucher authored
Adds additional gfx configuration data. v2: fix typo Acked-by:
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Jerry (Fangzhi) Zuo authored
Retrieve fuses to determine the availability of pipes, and eliminate pipes that cannot be used. Acked-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
Acked-by:
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Feifei Xu authored
Signed-off-by:
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Jerry (Fangzhi) Zuo authored
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Roman Li authored
Updating dce12 register headers by adding dc registers required for potential DP LTTPR support. v2: fix mode change Acked-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Feifei Xu authored
v2: fix whitespace Signed-off-by:
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Feifei Xu authored
Reviewed-by:
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Feifei Xu authored
Some register offset in nbio v7.4 are different with v7.0. v2: Use nbio7.0 for now. TODO: add a new nbio 7.4 module (Alex) Signed-off-by:
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Feifei Xu authored
Same as vega10 now. v2: squash in typo fix Reviewed-by:
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Feifei Xu authored
Vega20 need a seperate vega20_reg_init.c due to ip base offset difference. Reviewed-by:
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