- 16 May, 2018 1 commit
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Jacopo Mondi authored
Describe CEU0 peripheral for Renesas R-Mobile A1 R8A7740 Soc. Reported-by:
Geert Uytterhoeven <geert@glider.be> Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> [simon: dropped clock-names property] Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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- 14 May, 2018 14 commits
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Geert Uytterhoeven authored
Enable support for the ARM Performance Monitor Units in the Cortex-A7 CPU cores on RZ/G1E by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available Signed-off-by: -
Geert Uytterhoeven authored
Enable support for the ARM Performance Monitor Units in the Cortex-A15 CPU cores on RZ/G1M by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available Signed-off-by: -
Geert Uytterhoeven authored
Enable support for the ARM Performance Monitor Units in the Cortex-A7 CPU cores on R-Car E2 by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available Signed-off-by: -
Geert Uytterhoeven authored
Enable support for the ARM Performance Monitor Units in the Cortex-A15 CPU cores on R-Car M2-N by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available Signed-off-by: -
Geert Uytterhoeven authored
Enable support for the ARM Performance Monitor Units in the Cortex-A15 CPU cores on R-Car V2H by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available Signed-off-by: -
Geert Uytterhoeven authored
Enable support for the ARM Performance Monitor Units in the Cortex-A15 CPU cores on R-Car M2-W by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available Signed-off-by: -
Geert Uytterhoeven authored
Enable support for the ARM Performance Monitor Units in the Cortex-A15 and Cortex-A7 CPU cores on R-Car H2 by adding device nodes for the two PMUs. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available hw perfevents: /pmu-1: failed to probe PMU! hw perfevents: /pmu-1: failed to register PMU devices! The last two lines are due to the Cortex-A7 CPU cores being described in DT, but not enabled by the firmware. Signed-off-by: -
Geert Uytterhoeven authored
Enable support for the ARM Performance Monitor Units in the Cortex-A9 CPU core on RZ/A1H by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available Signed-off-by: -
Geert Uytterhoeven authored
According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware User's Manual rev. 3.00, the realtime clock interrupts are level not edge interrupts. Signed-off-by: -
Geert Uytterhoeven authored
According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware User's Manual rev. 3.00, the watchdog timer interrupt is a level interrupt. Signed-off-by: -
Geert Uytterhoeven authored
The PMU node references two interrupts, but lacks the interrupt-affinity property, which is required in that case: hw perfevents: no interrupt-affinity property for /pmu, guessing. Add the missing property to fix this. Signed-off-by: -
Geert Uytterhoeven authored
The PMU node references two interrupts, but lacks the interrupt-affinity property, which is required in that case: hw perfevents: no interrupt-affinity property for /pmu, guessing. Add the missing property to fix this. Signed-off-by: -
Geert Uytterhoeven authored
R-Mobile APE6 (r8a73a4) contains four Cortex-A15 and four Cortex-A7 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", so GIC interrupts are delivered to all 8 processor cores. Signed-off-by:
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Geert Uytterhoeven authored
R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts can be delivered to all 8 processor cores. Signed-off-by:
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- 08 May, 2018 1 commit
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Wolfram Sang authored
Same EEPROM as on Koelsch, et al. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
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- 02 May, 2018 7 commits
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Simon Horman authored
The gpio_keys node does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/emev2-kzm9d.dtb: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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Simon Horman authored
The vin port node does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7794-silk.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by:
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Simon Horman authored
The vin port node does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7794-alt.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by:
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Simon Horman authored
The vin port nodes does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7791-koelsch.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/boot/dts/r8a7791-koelsch.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef1000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by:
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Simon Horman authored
The vin port nodes does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7793-gose.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/boot/dts/r8a7793-gose.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef1000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by:
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Simon Horman authored
The vin port node does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7791-porter.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef0000/port: unnecessary #address-cells/#size-cells without Signed-off-by:
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Simon Horman authored
The vin port node does not have an address and thus does not need address-cells or address size-properties. This is flagged by dtc as follows: # make dtbs W=1 arch/arm/boot/dts/r8a7790-lager.dtb: Warning (avoid_unnecessary_addr_size): /soc/video@e6ef1000/port: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by:
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- 01 May, 2018 1 commit
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Kieran Bingham authored
Commit 5d3b50d3 ("ARM: dts: renesas: r8a7790: Add FDP1 instances") introduced the FDP1 for the r8a7790, but broke the sort ordering of the device tree nodes. Move the last VSP up to it's peers to correct the ordering. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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- 30 Apr, 2018 2 commits
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Biju Das authored
Define the iW-RainboW-G23S board dependent part of the EtherAVB device node. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Chris Paterson <chris.paterson2@renesas.com> Signed-off-by:
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Biju Das authored
Define the generic R8A77470 part of the EtherAVB device node. Signed-off-by:
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- 25 Apr, 2018 14 commits
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Laurent Pinchart authored
The r8a7790 has three FDP1 instances. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by:
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Biju Das authored
Add SCIF DMA support for R8A77470 SoC. Signed-off-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
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Biju Das authored
Describe SCIF ports in the R8A77470 device tree. Also it fixes the CPG clock index ZS from 6 to 5. Fixes: 6929dfc5 ("ARM: dts: r8a77470: Initial SoC device tree") Signed-off-by:
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Geert Uytterhoeven authored
Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by:
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Geert Uytterhoeven authored
Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by:
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Geert Uytterhoeven authored
Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by:
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Geert Uytterhoeven authored
Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by:
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Geert Uytterhoeven authored
Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by:
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Geert Uytterhoeven authored
Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by:
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Geert Uytterhoeven authored
Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by:
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Geert Uytterhoeven authored
Enable the watchdog, so the board can be restarted by a watchdog timeout. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the Watchdog Timer (WDT) controller on the Renesas R-Car M2-N (r8a7793) SoC. Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the Watchdog Timer (WDT) controller on the Renesas R-Car V2H (r8a7792) SoC. Signed-off-by:
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Fabrizio Castro authored
This patch enables the watchdog from within the iwg20m SoM dtsi. Signed-off-by:
Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Reviewed-by:
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