- 28 Mar, 2023 10 commits
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Jagan Teki authored
DSI host registration, attach and detach operations are quite different for the component and bridge-based DRM drivers. Supporting generic bridge driver to use both component and bridge based DRM drivers can be tricky and would require additional host related operation hooks. Add host operation hooks for registering and unregistering Exynos and generic drivers, where Exynos hooks are used in existing Exynos component based DRM drivers and generic hooks are used in i.MX8M bridge based DRM drivers. Add host attach and detach operation hooks for Exynos component DRM drivers and those get invoked while DSI core host attach and detach gets called. Tested-by:
Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by:
Marek Vasut <marex@denx.de> Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Signed-off-by:
Inki Dae <inki.dae@samsung.com>
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Jagan Teki authored
Finding the right input bus format throughout the pipeline is hard so add atomic_get_input_bus_fmts callback and initialize with the proper input format from list of supported output formats. This format can be used in pipeline for negotiating bus format between the DSI-end of this bridge and the other component closer to pipeline components. List of Pixel formats are taken from, AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 3.7.4 Pixel formats Table 14. DSI pixel packing formats Reviewed-by:
Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by:
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Jagan Teki authored
LCDIF-DSIM glue logic inverts the HS/VS/DE signals and expecting the i.MX8M Mini/Nano DSI host to add additional Data Enable signal active low (DE_LOW). This makes the valid data transfer on each horizontal line. So, add additional bus flags DE_LOW setting via input_bus_flags for i.MX8M Mini/Nano platforms. Tested-by:
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Jagan Teki authored
Look like an explicit fixing up of mode_flags is required for DSIM IP present in i.MX8M Mini/Nano SoCs. At least the LCDIF + DSIM needs active low sync polarities in order to correlate the correct sync flags of the surrounding components in the chain to make sure the whole pipeline can work properly. On the other hand the i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 says. "13.6.3.5.2 RGB interface Vsync, Hsync, and VDEN are active high signals." i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 3.6.3.5.2 RGB interface i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 13.6.2.7.2 RGB interface both claim "Vsync, Hsync, and VDEN are active high signals.", the LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. No clear evidence about whether it can be documentation issues or something, so added proper comments on the code. Comments are suggested by Marek Vasut. Tested-by:
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Marek Szyprowski authored
Host transfer() in the DSI master will invoke only when the DSI commands are sent from DSI devices like DSI Panel or DSI bridges and this host the transfer wouldn't invoke for I2C-based-DSI bridge drivers. Handling DSI host initialization in transfer calls misses the controller setup for I2C configured DSI bridges. This patch updates the DSI host initialization by calling host to init from bridge pre_enable as the bridge pre_enable API is invoked by core as it is common across all classes of DSI device drivers. The host init during pre_enable is conditional and not invoked for Exynos as existing downstream drm panels and bridges in Exynos are expecting the host initialization during DSI transfer. Reviewed-by:
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Jagan Teki authored
Samsung MIPI DSIM controller is common DSI IP that can be used in various SoCs like Exynos, i.MX8M Mini/Nano/Plus. Add hw_type enum via platform_data so that accessing the different controller data between various platforms becomes easy and meaningful. Tested-by:
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Jagan Teki authored
Look like PLL PMS_P offset value varies between platforms that have Samsung DSIM IP. However, there is no clear evidence for it as both Exynos and i.MX 8M Mini Application Processor Reference Manual is still referring the PMS_P offset as 13. The offset 13 is not working for i.MX8M Mini SoCs but the downstream NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms [1] [2]. PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P() with offset 13 and then an additional offset of one bit added in sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS(). Not sure whether it is reference manual documentation or something else but this patch trusts the downstream code and handle PLL_P offset via platform driver data so-that imx8mm driver data shall use pll_p_offset to 14. Similar to Mini the i.MX8M Nano/Plus also has P=14, unlike Exynos. [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n210 [2] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211Tested-by:
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Jagan Teki authored
The same Samsung MIPI DSIM master can also be used in NXP's i.MX8M Mini/Nano/Plus SoC. In i.MX8M Mini/Nano/Plus SoC the DSI Phy requires a MIPI DPHY bit to reset in order to activate the PHY and that can be done via upstream i.MX8M blk-ctrl driver. So, mark the phy get as optional. Tested-by:
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Jagan Teki authored
In general, for MIPI DSI there are three ways to represent the pipeline for an upstream bridge to find the connected downstream panel or bridge. 1. Child panel or bridge as a conventional device tree child node. 2. Child panel or bridge as an OF-graph port node. 3. Child panel or bridge as an OF-graph ports node. There are three different downstream panels or bridges that are possible to connect an upstream DSI host bridge - DSI Panel, DSI Bridge, and I2C-Configured DSI bridge. An example of the downstream panel represented as a child node, &dsi { compatible = "samsung,exynos5433-mipi-dsi"; ports { port@0 { reg = <0>; dsi_to_mic: endpoint { remote-endpoint = <&mic_to_dsi>; }; }; }; panel@0 { reg = <0>; }; }; An example of the downstream bridge represented as a port node, &i2c4 { bridge@2c { compatible = "ti,sn65dsi84"; ports { port@0 { reg = <0>; bridge_in_dsi: endpoint { remote-endpoint = <&dsi_out_bridge>; data-lanes = <1 2>; }; }; port@2 { reg = <2>; bridge_out_panel: endpoint { remote-endpoint = <&panel_out_bridge>; }; }; }; }; }; &dsi { compatible = "fsl,imx8mm-mipi-dsim"; port { dsi_in_lcdif: endpoint@0 { reg = <0>; remote-endpoint = <&lcdif_out_dsi>; }; dsi_out_bridge: endpoint@1 { reg = <1>; remote-endpoint = <&bridge_in_dsi>; }; }; }; An example of the downstream bridge represented as a ports node, &dsi { compatible = "fsl,imx8mm-mipi-dsim"; ports { port@0 { reg = <0>; dsi_in_lcdif: endpoint@0 { reg = <0>; remote-endpoint = <&lcdif_out_dsi>; }; }; port@1 { reg = <1>; dsi_out_bridge: endpoint { remote-endpoint = <&bridge_in_dsi>; }; }; }; In, summary it is possible to represent all three downstream slaves devices using OF-graph port or ports node however only DSI Panel and DSI Bridge are possible but not possible to represent I2C-Configured DSI bridge child nodes since I2C-Configure bridges are child of I2C node, not upstream DSI host bridge and it is must represent them endpoint port linking. This indeed means, the OF-graph port or ports representation is mandatory for I2C-Configured DSI bridges. This patch tries to add an OF-graph port or ports representation detection code on top of existing child node detection. It is possible to replace the entire detection code using existing drm_of helper drm_of_find_panel_or_bridge but it will break the Exynos DSI since the pipeline doesn't support OF-graph port or ports node. Overall, this patch has a combination of child and OF-graph pipeline detections in order to support the backward compatibility of Exynos DSI child node and i.MX8M Mini/Nano/Plus OF-graph port or ports node pipelines. This is the first common DSI host bridge driver that needs to support all possible downstream connection pipeline combinations. Tested-by: -
Jagan Teki authored
Exynos DSI already converted into a bridge driver, so bridge detach will suppose happened during bridge chain removal done by the bridge core. Drop the explicit call chain to detach the bridge. Tested-by:
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- 27 Mar, 2023 1 commit
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Daniel Vetter authored
Merge tag 'drm-rcar-next-20230325' of git://git.kernel.org/pub/scm/linux/kernel/git/pinchartl/linux into drm-next Miscellaneous fixes and improvements for rcar-du Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230325204922.GD19335@pendragon.ideasonboard.com
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- 25 Mar, 2023 8 commits
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Dan Carpenter authored
The drmm_encoder_alloc() function returns error pointers. It never returns NULL. Fix the check accordingly. Fixes: 7a1adbd2 ("drm: rcar-du: Use drmm_encoder_alloc() to manage encoder") Signed-off-by:
Dan Carpenter <error27@gmail.com> Reviewed-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Laurent Pinchart authored
The DORCR register controls the routing of clocks and data between DU channels within a group. For groups that contain a single channel, there's no routing option to control, and some fields of the register are then reserved. On Gen2 those reserved fields are documented as required to be set to 0, while on Gen3 and newer the PG1T, DK1S and PG1D reserved fields must be set to 1. The DU driver initializes the DORCR register in rcar_du_group_setup(), where it ignores the PG1T, DK1S and PG1D, and then configures those fields to the correct value in rcar_du_group_set_routing(). This hasn't been shown to cause any issue, but prevents certifying that the driver complies with the documentation in safety-critical use cases. As there is no reasonable change that the documentation will be updated to clarify that those reserved fields can be written to 0 temporarily before starting the hardware, make sure that the registers are always set to valid values. Signed-off-by:
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
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Laurent Pinchart authored
The DORCR fields were documented in the R-Car H1 datasheet with 1-based named, and then got renamed to 0-based in Gen2. The 0-based names are used for Gen3 and Gen4, making H1 an outlier. Rename the field macros to make them 0-based, in order to increase readability of the code when comparing it with the documentation. Signed-off-by:
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Laurent Pinchart authored
When the input to a DU channel comes from a VSP, the DU doesn't perform any blending operation. Select XRGB8888 instead of ARGB8888 to ensure that the corresponding registers don't get written with invalid values. Signed-off-by:
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Laurent Pinchart authored
The ESCR and OTAR registers are not present in all DU channels on Gen3 SoCs. ESCR only exists in channels that can be routed to an LVDS or DPAD, and OTAR in channels that can be routed to a DPAD. Skip writing those registers for other channels. This replaces the DU gen check, as Gen4 doesn't have LVDS or DPAD outputs. Signed-off-by:
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Laurent Pinchart authored
On R-Car D3 and E3, the LVDS encoder provides the dot (pixel) clock to the DU, regardless of whether the LVDS output is used or not. When using the DPAD (RGB) output, the DU driver thus enables and disables the LVDS PLL manually, while when using the LVDS output, it lets the LVDS bridge driver handle the PLL configuration internally as part of the atomic enable and disable operations. This causes an issue when using the LVDS output. As bridges are disabled before CRTCs, the current implementation violates the enable/disable sequences documented in the hardware datasheet, which requires the dot clock to be enabled before the CRTC is started and disabled after it gets stopped. Fix the problem by enabling/disabling the LVDS PLL manually from the DU regardless of which output is used, and skipping the PLL handling in the LVDS bridge atomic enable and disable operations. This is however not enough. Disabling the LVDS encoder while leaving the PLL on still results in a vertical blanking wait timeout when disabling the DU. Investigation showed that the culprit is the LVEN bit. For an unclear reason, clearing the bit when disabling the LVDS encoder blocks vertical blanking interrupts. We thus have to delay disabling the whole LVDS encoder, not just disabling the PLL, until the DU is disabled. We could split the LVDS disable sequence by clearing the LVRES bit in the LVDS bridge atomic disable handler, and delaying the rest of the operations, in order to disable the LVDS output at bridge atomic disable time, before stopping the CRTC. This would make the code more complex, without a clear benefit, so keep the implementation simple(r). Signed-off-by:
Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
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Laurent Pinchart authored
To prepare for a rework of the LVDS disable code, which will need to be called from rcar_lvds_pclk_disable(), move the LVDS enable code, currently stored in the __rcar_lvds_atomic_enable() function, to a separate code section separate from bridge operations. It will be then extended with the LVDS disable code. As part of this rework the __rcar_lvds_atomic_enable() function is renamed to rcar_lvds_enable() to more clearly indicate its purpose. No functional change intended. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
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Laurent Pinchart authored
When disabling the companion bridge in rcar_lvds_atomic_disable(), there's no need to go through the bridge's operations to call .atomic_disable(). Call rcar_lvds_atomic_disable() on the companion directly. Signed-off-by:
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- 24 Mar, 2023 2 commits
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git://anongit.freedesktop.org/drm/drm-intelDaniel Vetter authored
Core Changes: - drm: Add SDP Error Detection Configuration Register (Arun) Driver Changes: - Meteor Lake enabling and fixes (RK, Jose, Madhumitha) - Lock the fbdev obj before vma pin (Tejas) - DSC fixes (Stanislav) - Fixes and clean-up on opregion code (Imre) - More wm/vblank stuff (Ville) - More general display code organization (Jani) - DP Fixes (Stanislav, Ville) - Introduce flags to ignore long HPD and link training issues \ for handling spurious issues on CI (Vinod) - Plane cleanups and extra registers (Ville) - Update audio keepalive clock values (Clint) - Rename find_section to bdb_find_section (Maarten) - DP SDP CRC16 for 128b132b link layer (Arun) - Fix various issues with noarm register writes (Ville) - Fix a few TypeC / MST issues (Imre) - Create GSC submission targeting HDCP and PXP usages on MTL+ (Suraj) - Enable HDCP2.x via GSC CS (Suraj) Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDaniel Vetter authored
drm-misc-next for v6.4-rc1: Core Changes: - Add unit test for xrgb8888 to mono. - Assorted small fixes to format helper selftests. - Assorted documentation updates. - Drop drm_dev_set_unique. - Always use shadow buffer in generic fbdev emulation helpers, and improve error handling. Driver Changes: - Assorted small fixes to malidp, hdlcd, gma500, lima, bridge, rockchip. - Move fbdev in gma500 to use drm_client. - Convert bridge platform callbacks to void return. - Drop leftover from vgem to shmem helper conversion. Signed-off-by:
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- 23 Mar, 2023 6 commits
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Suraj Kandpal authored
MTL uses GSC command streamer i.e gsc cs to send HDCP/PXP commands to GSC f/w. It requires to keep hdcp display driver agnostic to content protection f/w (ME/GSC fw) in the form of i915_hdcp_fw_ops generic ops. Adding HDCP GSC CS interface by leveraging the i915_hdcp_fw_ops generic ops instead of I915_HDCP_COMPONENT as integral part of i915. Adding checks to see if GSC is loaded and proxy is setup --v6 -dont change the license date in same patch series [Jani] -fix the license year {Jani] --v8 -remove stale comment [Ankit] -get headers in alphabetical order [Ankit] -fix hdcp2_supported check [Ankit] --v9 -remove return statement from hdcp_gsc_fini [Ankit] Cc: Tomas Winkler <tomas.winkler@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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Suraj Kandpal authored
Add function that takes care of sending command to gsc cs. We start of with allocation of memory for our command intel_hdcp_gsc_message that contains gsc cs memory header as directed in specs followed by the actual payload hdcp message that we want to send. Spec states that we need to poll pending bit of response header around 20 times each try being 50ms apart hence adding that to current gsc_msg_send function Also we use the same function to take care of both sending and receiving hence no separate function to get the response. --v4 -Create common function to fill in gsc_mtl_header [Alan] -define host session bitmask [Alan] --v5 -use i915 directly instead of gt->i915 [Alan] -No need to make fields NULL as we are already using kzalloc [Alan] --v8 -change mechanism to reuse the same memory for one hdcp session[Alan] -fix header ordering -add comments to explain flags and host session mask [Alan] --v9 -remove gem obj from hdcp message as we can use i915_vma_unpin_and_release [Alan] -move hdcp message allocation and deallocation from hdcp2_enable and hdcp2_disable to init and teardown of HDCP [Alan] --v10 -remove unnecessary i915_vma_unpin [Alan] --v11 -fix comment style [Uma] Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Pervin Teres <alan.previn.teres.alexis@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:
Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by:
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Suraj Kandpal authored
It requires to move intel specific HDCP API structures to i915_hdcp_interface.h from driver/misc/mei/hdcp/mei_hdcp.h so that any content protection fw interfaces can use these structures. Cc: Tomas Winkler <tomas.winkler@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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Suraj Kandpal authored
There are more than 1 type of content protection security firmware. Make the name generic %s/_mei_/_ --v3 -Changing names to drop cp_fw to make naming more agnostic[Jani] --v4 -remove header reference in intel_display_core.h [Uma] -fix commit message and prefix drm [Uma] Cc: Tomas Winkler <tomas.winkler@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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Anshuman Gupta authored
pre MTL we interact with mei interface to talk to firmware and enable CP but going forward we will talk to gsc cs because of which we are making all names for HDCP helpers and structures generic as either mei or gsc cs maybe used. Change the include/drm/i915_mei_hdcp_interface.h to include/drm/i915_hdcp_interface.h Change the i915_hdcp_interface.h header naming convention to suit generic f/w type. %s/MEI_/HDCP_ %s/mei_dev/hdcp_dev Change structure name Accordingly. %s/i915_hdcp_comp_master/i915_hdcp_master %s/i915_hdcp_component_ops/i915_hdcp_ops --v6 -make each patch build individually [Jani] --v8 -change ME FW to ME/GSC FW [Ankit] -fix formatting issue [Ankit] --v9 -fix commit message and header [Uma] --v10 -rename comp variable [Uma] Cc: Tomas Winkler <tomas.winkler@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
Tomas Winkler <tomas.winkler@intel.com> Signed-off-by:
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Suraj Kandpal authored
HDCP and PXP will require a common function to allow it to submit commands to the gsc cs. Also adding the gsc mtl header that needs to be added on to the existing payloads of HDCP and PXP. --v4 -Seprate gsc load and heci cmd submission into different functions in different files for better scalability [Alan] -Rename gsc address field [Alan] --v5 -remove extra line is intel_gsc_fw.h [Uma] Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Signed-off-by: Suraj Kandpal<suraj.kandpal@intel.com> Reviewed-by:
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- 22 Mar, 2023 13 commits
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Alfredo Cruz authored
devm_regmap_init_mmio() may return an invalid pointer in case of an error. This patch adds the corresponding IS_ERR check to vop2->map. Signed-off-by:
Alfredo Cruz <alfredo.carlon@gmail.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20230322224411.15612-1-alfredo.carlon@gmail.com
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Toby Chen authored
This fixes a use-after-free crash during rmmod. The DRM encoder is embedded inside the larger rockchip_hdmi, which is allocated with the component. The component memory gets freed before the main drm device is destroyed. Fix it by running encoder cleanup before tearing down its container. Signed-off-by:
Toby Chen <tobyc@nvidia.com> [moved encoder cleanup above clk_disable, similar to bind-error-path] Signed-off-by:
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Tom Rix authored
clang reportes this error drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:2322:8: error: variable 'possible_crtcs' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized] if (vp) { ^~ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:2336:36: note: uninitialized use occurs here ret = vop2_plane_init(vop2, win, possible_crtcs); ^~~~~~~~~~~~~~ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:2322:4: note: remove the 'if' if its condition is always true if (vp) { ^~~~~~~~ The else-statement changes the win->type to OVERLAY without setting the possible_crtcs variable. Rework the block, initialize possible_crtcs to 0 to remove the else-statement. Split the else-if-statement out to its own if-statement so the OVERLAY check will catch when the win-type has been changed. Fixes: 368419a2 ("drm/rockchip: vop2: initialize possible_crtcs properly") Signed-off-by:Tom Rix <trix@redhat.com> Acked-by:
Michael Riesch <michael.riesch@wolfvision.net> Signed-off-by:
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Imre Deak authored
The current way to determine during HW state sanitization if a PHY is connected in the expected way doesn't work in all cases. The check for this considers only the PHY ready/owned state and the initial TC mode which was determined earlier by the TC port HW readout - using the sink's HPD and the same PHY ready/owned states. For instance for an enabled DP-alt/TBT port without the PHY ready/owned flags set the initial mode will be TBT, and this will be regarded as a valid PHY state. However it's possible that the port is actually enabled in DP-alt mode, but for some reason the PHY ownership was not acquired. Make sure the driver can detect invalid PHY states as in the above example by checking the PHY ready/owned state wrt. the PLL type used. This should be the TBT PLL if the PHY is not owned and the MG (non-TBT) PLL if the PHY is owned. v2: Rebased on change passing crtc_state in the previous patch. Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230321220101.983366-3-imre.deak@intel.com
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Imre Deak authored
For clarity factor out the function to determine if there are active links on a TC port. This prepares for the next patch also checking the port's PLL type. While at it pass crtc_state to intel_tc_port_sanitize_mode(), and check hw.active in that, instead of the deprecated crtc->active flag. v2: Check crtc_state->hw.active instead of crtc->active. (Ville) Reviewed-by:
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Imre Deak authored
Add an encoder hook, which can be called on enabled TC ports to determine if the port uses a TBT or a non-TBT PLL. An upcoming patch will use this to sanity check active TC port's PHY state wrt. the PLL type used by the port. Reviewed-by:
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Imre Deak authored
Since an HDMI output can only be enabled in legacy mode on TC ports, assume that VBT is wrong and the port is legacy if VBT says the port is non-legacy and has HDMI. If VBT says to enable DP as well leave the non-legacy flag enabled, relying on the flag getting fixed up based on the HPD status during sink detection. v2: Fix the legacy port flag only if DP is not enabled. Reviewed-by:
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Imre Deak authored
For consistency detect the initial TC mode in the PHY owned state the same way this is done in the not owned state (w/o changing the behavior). While at it, add more details to the PHY state debug print. Signed-off-by:
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Imre Deak authored
Atm, a TC port's initial mode will be read out as TBT mode in any case the PHY ownership is not held. This isn't correct for legacy ports which should be used only in legacy mode. Fix the above initial mode to be disconnected mode for a legacy port and TBT mode for DP-alt/TBT ports. Determine the port type by checking first the HPD state and then the legacy VBT flag (so the HPD state can correct a bogus VBT flag). If a sink is connected on a disabled port the PHY will get also connected (switching it to legacy mode on a legacy port). Also connect the PHY on a legacy port if it's enabled but BIOS incorrectly left it in the disconnected state for some reason. Signed-off-by:
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Imre Deak authored
A legacy TC port can't be switched to TBT mode, even if the PHY initialization wasn't ready yet for some reason, so prevent this. This shouldn't normally happen as the driver waits for the IOM/TCSS PHY initialization during driver loading and system resume. Signed-off-by:
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Imre Deak authored
Atm, the target TC mode - which the PHY should be switched to at any point it's used - is TBT in case there is no sink connected. However legacy ports are only used in the legacy mode regardless of the sink connected state. Fix the mode returned by intel_tc_port_get_target_mode() accordingly. Despite of the above issue, the PHY got disconnected as expected in response to a sink disconnect event, causing only a redundant PHY disconnect->reconnect sequence whenever the port was used. Signed-off-by:
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Imre Deak authored
Factor out helpers used later in the patchset to convert an HPD status mask to TC mode or target TC mode. No functional changes. Signed-off-by:
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Imre Deak authored
During boot-up/system resume, the TC PHY on legacy ports will be initialized by the IOM/TCSS firmware regardless of a sink being connected or not (as opposed to DP-alt/TBT ports, which the FW only inits once a sink is connected). Wait for the above initialization to complete during HW readout, so that connecting the PHY later will already see the expected PHY ready state. Signed-off-by:
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