- 25 Mar, 2022 2 commits
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Konrad Dybcio authored
The gpll4 postdiv is actually a div4, so make sure that Linux is aware of this. This fixes the following error messages: mmc1: Card appears overclocked; req 200000000 Hz, actual 343999999 Hz mmc1: Card appears overclocked; req 400000000 Hz, actual 687999999 Hz Fixes: aec89f78 ("clk: qcom: Add support for msm8994 global clock controller") Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220319174940.341137-1-konrad.dybcio@somainline.orgTested-by:
Petr Vorel <petr.vorel@gmail.com> Reviewed-by:
Stephen Boyd <sboyd@kernel.org>
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Ansuel Smith authored
qcom,gcc-other Documentation lacks a '|' for the description. This cause dt_binding_check to incorrectly parse "See also:" as a new value. Add the missing '|' to correctly parse the description. Fixes: a03965ed ("dt-bindings: clock: split qcom,gcc.yaml to common and specific schema") Signed-off-by:
Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20220323194248.26970-1-ansuelsmth@gmail.comReviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Reported-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 15 Mar, 2022 1 commit
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Stephen Boyd authored
Merge tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: This introduces support for A7 PLL on SDX65, GPU clock controller for SM6350, display clock controller for SM6125, SM6350 and QCS2290 and multimedia clock controller for MSM8226. The RPMCC drivers get support for SC8280XP and MSM8992, MSM8994 and MSM8998 gains some missing clocks. A new gcc DeviceTree binding is introduced, to allow platform-specific GCC bindings to inherit common properties. The SDM845 camera clock controller binding is converted to YAML. SDM845 camera clock controller, SDM660 GPU clock controller, IPQ8074 global clock controller, IPQ806x global clock controller, SC7180 camera and video clock controllers, MSM8996 globacl clock controller are converted to parent_data and/or parent_hws and cleanups related to this. Test clocks are removed from the SC7180, SDM845 camera clock controller drivers and SDM660 GPU clock controller driver. IPQ806x gains clocks and resets for CryptoEngine and additional frequencies for SDCC and NSS cores. Floor ops are introduced for RCG clocks and used for IPQ8074 SDCC clocks. SM8150 gains EMAC, PCIe and UFS GDSCs. The RCG2 logic for calculating D value is updated to support pixel clock frequencies on newer platforms. * tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (59 commits) clk: qcom: Add display clock controller driver for SM6125 dt-bindings: clock: add QCOM SM6125 display clock bindings clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig clk: qcom: gcc: Add emac GDSC support for SM8150 clk: qcom: gcc: sm8150: Fix some identation issues clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150 clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 clk: qcom: clk-rcg2: Update the frac table for pixel clock clk: qcom: clk-rcg2: Update logic to calculate D value for RCG clk: qcom: smd: Add missing MSM8998 RPM clocks clk: qcom: smd: Add missing RPM clocks for msm8992/4 dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks clk: qcom: gcc-ipq806x: add CryptoEngine resets dt-bindings: reset: add ipq8064 ce5 resets clk: qcom: gcc-ipq806x: add CryptoEngine clocks dt-bindings: clock: add ipq8064 ce5 clk define clk: qcom: gcc-ipq806x: add additional freq for sdc table clk: qcom: clk-rcg: add clk_rcg_floor_ops ops clk: qcom: gcc-ipq806x: add unusued flag for critical clock clk: qcom: gcc-ipq806x: add additional freq nss cores ...
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- 09 Mar, 2022 11 commits
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Martin Botka authored
Add support for the display clock controller found on SM6125 based devices. This allows display drivers to probe and control their clocks. Signed-off-by:
Martin Botka <martin.botka@somainline.org> Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220303131812.302302-4-marijn.suijten@somainline.org
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Martin Botka authored
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6125 SoC. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by:
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Marijn Suijten authored
In order to keep at least the list of `CONFIG_SM_` drivers sorted alphabetically, SDX_GCC_65 should have been moved one line up. This in turn makes it easier and cleaner to add the followup SM_DISPCC_6125 driver in the right place, right before SM_DISPCC_8250. Fixes: d79afa20 ("clk: qcom: Add SDX65 GCC support") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Bhupesh Sharma authored
Add the EMAC GDSC defines and driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
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Bhupesh Sharma authored
Fix identation issues with usb30 gdsc structs in gcc-sm8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Bhupesh Sharma authored
Add the UFS_CARD and UFS_PHY GDSC defines & driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Bhupesh Sharma authored
Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Taniya Das authored
Support the new numerator and denominator for pixel clock on SM8350 and support rgb101010, RGB888 use cases on SM8450. Fixes: 99cbd064 ("clk: qcom: Support display RCG clocks") Signed-off-by:
Taniya Das <tdas@codeaurora.org> Reviewed-by:
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Taniya Das authored
The display pixel clock has a requirement on certain newer platforms to support M/N as (2/3) and the final D value calculated results in underflow errors. As the current implementation does not check for D value is within the accepted range for a given M & N value. Update the logic to calculate the final D value based on the range. Fixes: 99cbd064 ("clk: qcom: Support display RCG clocks") Signed-off-by:
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Konrad Dybcio authored
Add missing RPM-provided clocks on msm8998 and reorder the definitions where needed. Tested-by:
Jami Kettunen <jami.kettunen@somainline.org> Signed-off-by:
Caleb Connolly <caleb@connolly.tech> Signed-off-by:
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Konrad Dybcio authored
XO and MSS_CFG were omitted when first adding the clocks for these SoCs. Add them, and while at it, move the XO clock to the top of the definition list, as ideally everyone should start using it sooner or later.. Fixes: b4297844 ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks") Signed-off-by:
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- 08 Mar, 2022 22 commits
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Konrad Dybcio authored
Add the missing clock definitions. Signed-off-by:
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Ansuel Smith authored
Add missing CryptoEngine resets. Signed-off-by:
Jonathan McDowell <noodles@earth.li> Signed-off-by:
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Ansuel Smith authored
Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
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Ansuel Smith authored
Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by:
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Ansuel Smith authored
Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. Define CE5_SRC is not used so it's OK to change and we align it to the QSDK naming. Signed-off-by:
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Ansuel Smith authored
Add additional freq supported for the sdc table. The ops are changed to the floor_ops to handle a freq request of 52kHz where we need to provide a freq of 51.2kHz instead for stability reason. Signed-off-by:
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Ansuel Smith authored
Add clk_rcg_floor_ops for clock that can't provide a stable freq and require to use a floor freq to provide the requested frequency. Signed-off-by:
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Ansuel Smith authored
Some clocks are used by other devices present on the SoC. For example the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to reject any regulator change command. These clock should never be disabled. Signed-off-by:
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Ansuel Smith authored
Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be clocked to 800MHz. Add these missing freq to the gcc driver. Set the freq_tbl for the ubi32_cores to the correct values based on the machine compatible. Signed-off-by:
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Ansuel Smith authored
Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by:
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Ansuel Smith authored
Convert parent_names to parent_data to modernize the driver. Where possible use parent_hws directly. Signed-off-by:
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Ansuel Smith authored
Parent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error. Signed-off-by:
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Ansuel Smith authored
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc. Use qcom,gcc.yaml as a template and remove the compatible from generic qcom,gcc-other.yaml Signed-off-by:
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Ansuel Smith authored
Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a template and remove the compatible from qcom,gcc.yaml Signed-off-by:
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Ansuel Smith authored
Split qcom,gcc.yaml to common and specific schema to use it as a template for schema that needs to use the gcc bindings and require to add additional bindings. Signed-off-by:
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Rohit Agarwal authored
Update APCS Kconfig to reflect support for SDX65 APCS clock controller. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Rohit Agarwal authored
Update A7 PLL Kconfig to reflect support for SDX65. Signed-off-by:
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Rohit Agarwal authored
Add information for Cortex A7 PLL clock in Qualcomm platform SDX65. Signed-off-by:
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Konrad Dybcio authored
Add support for the GPU clock controller found on SM6350. Signed-off-by:
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Konrad Dybcio authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6350 SoCs. Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Add support for the display clock controller found on SM6350. Signed-off-by:
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Konrad Dybcio authored
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6350 SoC. Signed-off-by:
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- 25 Feb, 2022 2 commits
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Bjorn Andersson authored
The Qualcomm SC8280XP platform exposes 5 clocks through the RPMh clock controller. Add these, and the relates active-only variants, to the RPMh clock controller driver. Signed-off-by:
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Bjorn Andersson authored
The Qualcomm SC8280XP has a RPMh clock controller, so add a compatible for this to the binding. Signed-off-by:
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- 24 Feb, 2022 2 commits
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Dirk Buchwalder authored
Use floor ops on SDCC1 APPS clock in order to round down selected clock frequency and avoid overclocking SD/eMMC cards. For example, currently HS200 cards were failling tuning as they were actually being clocked at 384MHz instead of 192MHz. This caused some boards to disable 1.8V I/O and force the eMMC into the standard HS mode (50MHz) and that appeared to work despite the eMMC being overclocked to 96Mhz in that case. There was a previous commit to use floor ops on SDCC clocks, but it looks to have only covered SDCC2 clock. Fixes: 9607f622 ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks") Signed-off-by:
Dirk Buchwalder <buchwalder@posteo.de> Signed-off-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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Dmitry Baryshkov authored
The driver can parse bi-tcxo clock from the clocks passed in the device tree. Specify it in schema. Signed-off-by:
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