1. 04 Jul, 2011 1 commit
    • Stephen Warren's avatar
      ASoC: Tegra: I2S: Ensure clock is enabled when writing regs · 713d1369
      Stephen Warren authored
      The I2S controller needs a clock to respond to register writes. Without
      this, register writes will at worst hang the CPU. In practice, I've only
      observed writes being dropped.
      
      Luckily, the dropped register writes historically had no effect:
      
      TEGRA_I2S_TIMING: The value we wrote was the reset default.
      
      TEGRA_I2S_FIFO_SCR: The default was for the FIFOs to request more data
      when one slot was empty. The requested value was for the FIFOs to request
      when four slots were empty. The DMA controller in the mainline kernel is
      configured to burst a single entry at a time into the FIFO, hence there
      was no issue. The only negative effect was on bus efficiency losses due
      to an increased number of arbitration attempts.
      
      However, in various non-upstream changes, the DMA controller now bursts
      four entries at a time into the FIFO. If there is only space for one
      entry, the data is simply dropped. In practice, this resulted in 3/4 of
      samples being dropped, and playback at 4x the expected rate and pitch.
      By fixing the clocking issue, this is solved.
      Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      Acked-by: default avatarLiam Girdwood <lrg@ti.com>
      Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
      713d1369
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